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Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux

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This commit is contained in:
David Biancolin
2020-09-25 10:52:33 -07:00
parent 67145c6ccd 023d8096a9
commit b76972d34b
20 changed files with 218 additions and 333 deletions
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10
generators/chipyard/src/main/scala/Clocks.scala
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@@ -60,16 +60,15 @@ object GenerateReset {
val reset_wire = Wire(Input(Reset()))
val (reset_io, resetIOCell) = p(GlobalResetSchemeKey) match {
case GlobalResetSynchronous =>
IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"))
IOCell.generateIOFromSignal(reset_wire, "reset")
case GlobalResetAsynchronousFull =>
IOCell.generateIOFromSignal(reset_wire, Some("iocell_reset"), abstractResetAsAsync = true)
IOCell.generateIOFromSignal(reset_wire, "reset", abstractResetAsAsync = true)
case GlobalResetAsynchronous => {
val async_reset_wire = Wire(Input(AsyncReset()))
reset_wire := ResetCatchAndSync(clock, async_reset_wire.asBool())
IOCell.generateIOFromSignal(async_reset_wire, Some("iocell_reset"), abstractResetAsAsync = true)
IOCell.generateIOFromSignal(async_reset_wire, "reset", abstractResetAsAsync = true)
}
}
reset_io.suggestName("reset")
chiptop.iocells ++= resetIOCell
chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
reset_io := th.dutReset
@@ -124,9 +123,8 @@ object ClockingSchemeGenerators {
InModuleBody {
val clock_wire = Wire(Input(Clock()))
val reset_wire = GenerateReset(chiptop, clock_wire)
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, Some("iocell_clock"))
val (clock_io, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock")
chiptop.iocells ++= clockIOCell
clock_io.suggestName("clock")
referenceClockSource.out.unzip._1.map { o =>
o.clock := clock_wire

2
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -16,7 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port
with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART
with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs
with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller

24
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -223,20 +223,24 @@ class WithTiedOffDebug extends OverrideHarnessBinder({
})
class WithTiedOffSerial extends OverrideHarnessBinder({
(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p => SerialAdapter.tieoff(Some(p.bits)) }
Nil
class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser)
})
}
})
class WithSimSerial extends OverrideHarnessBinder({
(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
val ser_success = SerialAdapter.connectSimSerial(p.bits, p.clock, th.harnessReset)
when (ser_success) { th.success := true.B }
}
Nil
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, port.clock, th.harnessReset.asBool)
when (success) { th.success := true.B }
})
}
})

27
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -146,8 +146,7 @@ class WithGPIOCells extends OverrideIOBinder({
class WithUARTIOCells extends OverrideIOBinder({
(system: HasPeripheryUARTModuleImp) => {
val (ports: Seq[UARTPortIO], cells2d) = system.uart.zipWithIndex.map({ case (u, i) =>
val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}"), system.p(IOCellKey))
port.suggestName(s"uart_${i}")
val (port, ios) = IOCell.generateIOFromSignal(u, s"uart_${i}", system.p(IOCellKey))
(port, ios)
}).unzip
(ports, cells2d.flatten)
@@ -158,8 +157,9 @@ class WithUARTIOCells extends OverrideIOBinder({
class WithSPIIOCells extends OverrideIOBinder({
(system: HasPeripherySPIFlashModuleImp) => {
val (ports: Seq[SPIChipIO], cells2d) = system.qspi.zipWithIndex.map({ case (s, i) =>
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"spi_${i}")
val iocellBase = s"iocell_spi_${i}"
val name = s"spi_${i}"
val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(name)
val iocellBase = s"iocell_${name}"
// SCK and CS are unidirectional outputs
val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck"), system.p(IOCellKey))
@@ -185,8 +185,7 @@ class WithSPIIOCells extends OverrideIOBinder({
class WithExtInterruptIOCells extends OverrideIOBinder({
(system: HasExtInterruptsModuleImp) => {
if (system.outer.nExtInterrupts > 0) {
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts"), system.p(IOCellKey))
port.suggestName("ext_interrupts")
val (port: UInt, cells) = IOCell.generateIOFromSignal(system.interrupts, "ext_interrupts", system.p(IOCellKey))
(Seq(port), cells)
} else {
(Nil, Nil)
@@ -230,19 +229,16 @@ class WithDebugIOCells extends OverrideIOBinder({
// Add IOCells for the DMI/JTAG/APB ports
val dmiTuple = debug.clockeddmi.map { d =>
IOCell.generateIOFromSignal(d, Some("iocell_dmi"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
IOCell.generateIOFromSignal(d, "dmi", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
}
dmiTuple.map(_._1).foreach(_.suggestName("dmi"))
val jtagTuple = debug.systemjtag.map { j =>
IOCell.generateIOFromSignal(j.jtag, Some("iocell_jtag"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
IOCell.generateIOFromSignal(j.jtag, "jtag", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
}
jtagTuple.map(_._1).foreach(_.suggestName("jtag"))
val apbTuple = debug.apb.map { a =>
IOCell.generateIOFromSignal(a, Some("iocell_apb"), p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
IOCell.generateIOFromSignal(a, "apb", p(IOCellKey), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)
}
apbTuple.map(_._1).foreach(_.suggestName("apb"))
val allTuples = (dmiTuple ++ jtagTuple ++ apbTuple).toSeq
(allTuples.map(_._1).toSeq, allTuples.flatMap(_._2).toSeq)
@@ -250,11 +246,10 @@ class WithDebugIOCells extends OverrideIOBinder({
}
})
class WithSerialIOCells extends OverrideIOBinder({
(system: CanHavePeripherySerial) => system.serial.map({ s =>
class WithSerialTLIOCells extends OverrideIOBinder({
(system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
val sys = system.asInstanceOf[BaseSubsystem]
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, Some("serial"), sys.p(IOCellKey))
port.suggestName("serial")
val (port, cells) = IOCell.generateIOFromSignal(s.getWrappedValue, "serial_tl", sys.p(IOCellKey))
(Seq(port), cells)
}).getOrElse((Nil, Nil))
})

4
generators/chipyard/src/main/scala/Subsystem.scala
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@@ -25,12 +25,12 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile}
import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}
import testchipip.{DromajoHelper, CanHavePeripheryTLSerial, SerialTLKey}
trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
case _: CanHavePeripherySerial if p(SerialKey) => true
case _: CanHavePeripheryTLSerial if p(SerialTLKey).nonEmpty => true
case _: HasPeripheryDebug if p(ExportDebug).dmi => true
case _ => false
}) {

2
generators/chipyard/src/main/scala/clocking/ClockDividerN.scala
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@@ -1,4 +1,4 @@
// See LICENSE.SiFive for license details.
// See LICENSE for license details.
package chipyard.clocking

7
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -14,8 +14,8 @@ class AbstractConfig extends Config(
// The HarnessBinders control generation of hardware in the TestHarness
new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
new chipyard.harness.WithSimSerial ++ // add external serial-adapter and RAM
new chipyard.harness.WithSimDebug ++ // add SimJTAG or SimDTM adapters if debug module is enabled
new chipyard.harness.WithSimSerial ++ // add SimSerial adapter for HTIF, if serial port is present
new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present
new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled
new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled
@@ -29,7 +29,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
new chipyard.iobinders.WithNICIOPunchthrough ++
new chipyard.iobinders.WithSerialIOCells ++
new chipyard.iobinders.WithSerialTLIOCells ++
new chipyard.iobinders.WithDebugIOCells ++
new chipyard.iobinders.WithUARTIOCells ++
new chipyard.iobinders.WithGPIOCells ++
@@ -38,8 +38,7 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithTraceIOPunchthrough ++
new chipyard.iobinders.WithExtInterruptIOCells ++
new testchipip.WithTSI ++ // use testchipip serial offchip link
new testchipip.WithDefaultSerialTL ++ // use serialized tilelink port to external serialadapter/harnessRAM
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs

2
generators/chipyard/src/main/scala/config/ArianeConfigs.scala
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@@ -13,7 +13,7 @@ class ArianeConfig extends Config(
new chipyard.config.AbstractConfig)
class dmiArianeConfig extends Config(
new chipyard.harness.WithTiedOffSerial ++ // Tie off the serial port, override default instantiation of SimSerial
new chipyard.harness.WithSerialAdapterTiedOff ++ // Tie off the serial port, override default instantiation of SimSerial
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new ariane.WithNArianeCores(1) ++ // single Ariane core
new chipyard.config.AbstractConfig)

8
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -25,7 +25,7 @@ class GemminiRocketConfig extends Config(
// DOC include start: DmiRocket
class dmiRocketConfig extends Config(
new chipyard.harness.WithTiedOffSerial ++ // don't use serial to drive the chip, since we use DMI instead
new chipyard.harness.WithSerialAdapterTiedOff ++ // don't attach an external SimSerial
new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
@@ -179,3 +179,9 @@ class DividedClockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class LBWIFRocketConfig extends Config(
new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

5
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -66,9 +66,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
})
class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
SerialBridge(p.clock, p.bits, MainMemoryConsts.globalName)(GetSystemParameters(system))
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset)
SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system))
}
Nil
}

4
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -84,7 +84,7 @@ class WithFireSimConfigTweaks extends Config(
// Required: Adds IO to attach SerialBridge. The SerialBridges is responsible
// for signalling simulation termination under simulation success. This fragment can
// be removed if you supply an auxiliary bridge that signals simulation termination
new testchipip.WithTSI ++
new testchipip.WithDefaultSerialTL ++
// Optional: Removing this will require using an initramfs under linux
new testchipip.WithBlockDevice ++
// Required*: Scale default baud rate with periphery bus frequency
@@ -131,7 +131,7 @@ class FireSimSmallSystemConfig extends Config(
new WithoutClockGating ++
new WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithExtMemSize(1 << 28) ++
new testchipip.WithTSI ++
new testchipip.WithDefaultSerialTL ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUART ++
new freechips.rocketchip.subsystem.WithInclusiveCache(nWays = 2, capacityKB = 64) ++

2
generators/testchipip

Submodule generators/testchipip updated: a86c827ca6...bdca33ec16