[clocks] Fix comment in ClockDividerN

2020-09-17 11:32:51 -07:00
parent b8d3e4a66d
commit cfa7e30d95
1 changed files with 1 additions and 1 deletions
--- a/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv
+++ b/generators/chipyard/src/main/resources/vsrc/ClockDividerN.sv
@@ -2,7 +2,7 @@

 /**
  * An unsynthesizable divide-by-N clock divider.
-  * Duty cycle is 100 * (ceil(DIV / 2)) / 2.
+  * Duty cycle is 100 * (ceil(DIV / 2)) / DIV.
  */

 module ClockDividerN #(parameter DIV)(output logic clk_out = 1'b0, input clk_in);