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Bump to support firesim simulation of no-AXI4DRAM designs

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This commit is contained in:
Jerry Zhao
2020-10-01 10:21:43 -07:00
parent 164617e2d6
commit 79042e4ce8
2 changed files with 6 additions and 5 deletions
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9
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -9,7 +9,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.amba.axi4.{AXI4Bundle}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart._
@@ -67,9 +67,10 @@ class WithFireSimIOCellModels extends Config((site, here, up) => {
class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { p =>
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, p, th.harnessReset)
SerialBridge(p.clock, ram.module.io.tsi_ser, MainMemoryConsts.globalName)(GetSystemParameters(system))
ports.map { port =>
implicit val p = GetSystemParameters(system)
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset)
SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
}
Nil
}