wu-arch/radiance
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
593 Commits 3 Branches 0 Tags
5a79d7ff79c50da4f30f12cccdc93725d25e400a
Commit Graph

518 Commits

Author SHA1 Message Date
Hansung Kim
e96836c190 Fix inflightCounter debug counter 2024-01-18 01:06:28 -08:00
Hansung Kim
138e83b68a Assert coreWriteReqQueue is never full in VortexCache 2024-01-18 01:05:23 -08:00
Hansung Kim
7914607304 Bump vortex with IBUF/LSUQ size change 2024-01-16 23:54:39 -08:00
Hansung Kim
37d2af5478 Reflect upstream rocket-chip changes 
* hartId -> tileId
* TileCrossingParamsLike -> HierarchicalElementCrossingParamsLike
* don't use bus_error_unit
 2024-01-16 23:44:57 -08:00
Hansung Kim
cd1022c608 Remove use of HasTiles to reflect upstream change 2024-01-16 22:59:56 -08:00
Hansung Kim
132742ea88 Distinguish LSU lanes from SIMD lanes and elaborate tag width logic 2024-01-16 22:20:16 -08:00
Richard Yan
dea005a179 incorporate vortex2 2024-01-16 17:41:33 -08:00
Richard Yan
f9b7e9fbe4 restructure from rocket-chip to radiance 2024-01-16 16:21:50 -08:00
Richard Yan
c742a13c1e restructure: initial filter pass 2024-01-11 10:08:43 -08:00
Zekai Lin
ca57c8d6a3 TLFragmenter bug fix 2023-12-09 20:27:13 -08:00
Hansung Kim
0768a7abc9 More cleanup and doc 2023-11-10 18:49:11 -08:00
Hansung Kim
0bb8e6d705 Bump vortex with ibuffer size fix 2023-11-10 18:38:59 -08:00
Hansung Kim
ecfa18ce69 Rename to VortexBank 2023-11-10 17:46:04 -08:00
Hansung Kim
78e09160a2 Rename L1System -> VortexL1; do not expose bank Xbar from L1 2023-11-10 16:11:43 -08:00
Hansung Kim
257232dec8 Require MSHR size matches nSrcId to L2 2023-11-10 15:04:32 -08:00
Hansung Kim
5adf334af4 Scalafmt & rename & update doc 2023-11-10 14:58:16 -08:00
Hansung Kim
d51ce4cfa8 Reformat 2023-11-10 14:46:33 -08:00
Hansung Kim
17a39a369f Cleanup conditional L1 instantiation 2023-11-10 14:42:33 -08:00
Hansung Kim
a0c15b2cc3 Use separate {imem,dmem}SourceWidth to fix deadlock 
imemSourceWidth cannot be larger than the ibuffer size.
 2023-11-08 20:20:17 -08:00
Hansung Kim
2f205be702 Update docs 2023-11-08 14:03:14 -08:00
Hansung Kim
571d33a5de Remove unused MSB offset code from get getCoalescedDataChunk 2023-11-08 14:03:14 -08:00
Vamber Yang
61aad0315c L1 FatBank Integration, multi-bank working with 4 dcache banks, 1 icache bank 
Merge remote-tracking branch 'remotes/origin/graphics' into local-graphics-dev
 2023-11-06 21:56:11 -08:00
Vamber Yang
e958ede277 multi-bank working when nBanks=2, encountered a putPartial error, need to pull latest change 2023-11-06 20:51:23 -08:00
Vamber Yang
be5134cd8a L1 fatbank works with 2^5 source bits in SourceGen, failed with < 2^4 source bits in SourceGen 2023-11-01 23:48:24 -07:00
Hansung Kim
d2bfc31592 Fix store opcode assertion in AOpcodeIsStore 
Now we support PutPartialData for narrow write requests that doesn't have all-1
mask.
 2023-10-31 23:06:35 -07:00
Vamber Yang
75adb1dc66 Intergation of L1 Fatbank 2023-10-31 16:14:34 -07:00
Hansung Kim
635f4e42ff Add detailed doc on source allocation/filtering 2023-10-25 20:55:01 -07:00
Hansung Kim
6371cdc03c Use edge.hasData instead of TLUtils in adapter 2023-10-25 20:28:01 -07:00
Hansung Kim
1e8cc5ef90 Bump vortex 2023-10-25 20:07:20 -07:00
Hansung Kim
d70cbc8e58 Do matchingSources filtering using Vortex tag instead of TL source 
Since we do source generation independently for each lane, if we use TL
source for filtering, it becomes possible that lane 0's source happens
to match lane 1/2/3's source even when they don't belong to the same
warp.  Since Vortex uses dcache req ID that is unique across
instructions, using that for filtering prevents this bug.  A better
solution would be to do source generation for all lanes at a time
though.
 2023-10-25 19:48:21 -07:00
Hansung Kim
78e193db42 Add safety assert on sourceWidth 
See commit 0d92eb65.
 2023-10-25 18:17:03 -07:00
Hansung Kim
09f512fda7 Don't reply write requests from Vortex core 2023-10-25 13:08:18 -07:00
Hansung Kim
ba8bed6120 Set missing opcode field for uncoalesced requests 2023-10-25 13:07:54 -07:00
Hansung Kim
762e6dfd27 Rename queueDepth -> reqQueueDepth 2023-10-25 11:29:51 -07:00
Hansung Kim
f0a401d72b Add missing PutPartial mask handling for coalesced writes 2023-10-24 15:11:41 -07:00
Hansung Kim
3fc3e91831 Rename & doc 2023-10-24 14:04:00 -07:00
Hansung Kim
8affa755d0 Remove overly strict enq.ready assertion on respQueues 
This used to make sense when we used MemTraceCores which never blocks
the response channel, but now that we're integrating with Vortex cores,
we cannot make the same assumption on the core's actual pipeline
behavior (although it is unclear why a core would ever block receiving
responses.)
 2023-10-24 11:41:34 -07:00
Hansung Kim
e9c206dfa2 Properly handle upstream and downstream backpressure for respQueues 2023-10-24 11:36:18 -07:00
Hansung Kim
8e0904a1ad Fix matchingSources logic when all lanes are invalid 
When all lanes are invalid so that arb.io.valid is 0, we should not
deassert d_ready.
 2023-10-23 22:10:10 -07:00
Hansung Kim
a14d8b6814 Properly handle TL dataWidth mismatch for core-to-sbus configs 
... using yet another TLWidthWidget
 2023-10-23 20:33:41 -07:00
Hansung Kim
2e37d2ce3f Only check opcode validity when fire 
... otherwise assertion goes off with garbage-value opcode during reset.
 2023-10-23 20:31:00 -07:00
Hansung Kim
0f9896e001 Instantiate coalescer inside VortexTile 
Currently runtime errors with unhandled D opcode inside coalescer.
 2023-10-23 15:01:37 -07:00
Hansung Kim
2091ef686b Rename defaultConfig -> DefaultCoalescerConfig 2023-10-23 14:50:15 -07:00
Hansung Kim
105bb37421 Make VortexCoreParams; bring VortexTile into rocketchip.tile 
Reduces duplicate declarations.  Need to properly split it out of
rocket-chip later.
 2023-10-23 13:04:48 -07:00
Hansung Kim
f4553ffdb1 Remove done TODO 2023-10-23 11:33:38 -07:00
Vamber Yang
60a63d4e11 FatBank Integration Improvements: 
1. ensure FatBank prioritze Ack read over Ack write to downstream
   coalescer
2. Between FatBank and L2, use the new sourceGenerator to allow both Read and
   Write Reqs sharing the same pool of available src_ids
 2023-10-22 17:03:44 -07:00
Richard Yan
2a9f2f8421 fix typo 2023-10-19 17:10:56 -07:00
Richard Yan
77e3ad4934 Merge branch 'graphics' of https://github.com/hansungk/rocket-chip into graphics 2023-10-19 16:16:24 -07:00
Richard Yan
9d8e9de8d0 differentiate addresses for different harts 2023-10-19 16:14:35 -07:00
Hansung Kim
805abd1b4b Bump vortex for TL port change 2023-10-18 20:05:55 -07:00