Add safety assert on sourceWidth

See commit 0d92eb65.
2023-10-25 18:17:03 -07:00
parent 09f512fda7
commit 78e193db42
1 changed files with 4 additions and 0 deletions
--- a/src/main/scala/tile/VortexTile.scala
+++ b/src/main/scala/tile/VortexTile.scala
@@ -160,6 +160,10 @@ class VortexTile private (
    case Some(simtParam) => log2Ceil(simtParam.nSrcIds)
    case None => 4
  }
+  require(sourceWidth >= 4,
+    "Allocating a small number of sourceIds may cause correctness bug inside " +
+    "Vortex core due to unconstrained synchronization issues between warps." +
+    "We recommend setting nSrcIds to at least 16.")

  val imemNodes = Seq.tabulate(1) { i =>
    TLClientNode(Seq(TLMasterPortParameters.v1(