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differentiate addresses for different harts

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This commit is contained in:
Richard Yan
2023-10-19 16:14:35 -07:00
parent dd194ca61d
commit 9d8e9de8d0
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/tile/VortexTile.scala
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@@ -61,9 +61,9 @@ class VortexTile private(
val slaveNode = TLIdentityNode()
val masterNode = visibilityNode
val regDevice = new SimpleDevice("vortex-reg", Seq("vortex-reg"))
val regDevice = new SimpleDevice("vortex-reg", Seq(s"vortex-reg${tileParams.hartId}"))
val regNode = TLRegisterNode(
address = Seq(AddressSet(0x7c000000, 0xfff)),
address = Seq(AddressSet(0x7c000000 + 0x1000 * tileParams.hartId, 0xfff)),
device = regDevice,
beatBytes = 4,
concurrency = 1)
@@ -156,7 +156,7 @@ class VortexTile private(
val beuProperty = bus_error_unit.map(d => Map(
"sifive,buserror" -> d.device.asProperty)).getOrElse(Nil)
val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,vortex0", "riscv")) {
val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq(s"sifive,vortex${tileParams.hartId}", "riscv")) {
override def parent = Some(ResourceAnchors.cpus)
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)