Hansung Kim
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337272764b
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Test with Get() and doc source ID allocation
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2023-03-06 23:15:30 -08:00 |
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Hansung Kim
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760d3f5aa2
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Add example where IdentityNode.out has different data from .in
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2023-03-06 21:56:56 -08:00 |
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Hansung Kim
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c7651e26f4
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Organize Diplomacy node structure of CoalescingUnit
IdentityNode with numThreads edges + master TL node with additional 1
edge for the new coalesced requests.
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2023-03-06 16:17:52 -08:00 |
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Hansung Kim
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aa2d52a197
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Merge Coalescing{Logic, Entry} to CoalescingUnit
CoalescingUnit acts as the top module that abstracts TL wrangling away
from outside.
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2023-03-05 17:33:37 -08:00 |
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Hansung Kim
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6fea4be050
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Refactor with zip
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2023-03-05 16:59:06 -08:00 |
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Hansung Kim
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db9be56191
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Properly connect each lane to TL node
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2023-03-05 00:18:29 -08:00 |
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Hansung Kim
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ef1608505f
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Use single SimMemTrace instance
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2023-03-04 23:55:20 -08:00 |
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Hansung Kim
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172ab51355
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Fix formatting and unused warnings
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2023-03-03 23:44:50 -08:00 |
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Hansung Kim
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5f55a7578f
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Recover lost changes
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2023-03-03 22:36:54 -08:00 |
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Hansung Kim
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dcb49f7683
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Doc update
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2023-03-03 21:22:56 -08:00 |
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Vamber Yang
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c3129b8c5c
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Tracer supports N threads, communicates with Coalescing with TL + Diplomacy interface
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2023-03-03 20:27:29 -08:00 |
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Hansung Kim
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24f4ee93ac
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Add TL client node to MemTraceDriver
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2023-02-27 23:35:14 -08:00 |
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Hansung Kim
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a06b5faa3c
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Wrap memtrace DPI module with a Chisel driver module
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2023-02-27 19:55:22 -08:00 |
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Hansung Kim
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9025729c0e
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Emit address in addition to cycle
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2023-02-27 17:36:54 -08:00 |
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Hansung Kim
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0ebaed5f1b
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Communicate trace cycle data from C++ to Chisel
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2023-02-27 14:40:49 -08:00 |
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Hansung Kim
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72de4bca66
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Initial parsing of memory trace file in C++
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2023-02-27 13:47:30 -08:00 |
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Hansung Kim
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80e4b5c734
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Set up simple DPI for trace-driven testing
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2023-02-26 20:39:19 -08:00 |
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Hansung Kim
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5bf8bb8217
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Add empty unit test for coalescing unit
copied over from WithTLXbarUnitTests
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2023-02-22 16:42:18 -08:00 |
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