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33f7adb5eb8885d7294528b9dd0a3c2147fa5bb6
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Author SHA1 Message Date
Hansung Kim
33f7adb5eb Make separate param for response depth queue 
This is not necessarily the same as NUM_NEW_IDS, the latter determines
the inflight coalescing table size but not the response queues.
 2023-04-25 17:09:46 -07:00
Hansung Kim
980c77a8fa Renames 2023-04-25 16:55:59 -07:00
Hansung Kim
9000577f45 Add assertions for queue drift 2023-04-25 14:36:52 -07:00
Richard Yan
99348e1e40 mostly running coalescing test 2023-04-25 02:50:14 -07:00
Richard Yan
3a0fdb2c67 WIP diplomacy set up for coal unit test 2023-04-25 02:26:13 -07:00
Richard Yan
be40c77d06 merge graphics 2023-04-25 00:10:51 -07:00
Richard Yan
37620400db WIP coalescing flow test 2023-04-25 00:09:23 -07:00
Hansung Kim
31e04e9402 Fix CoalShiftQueue invalidate logic 
IO type change to Valid[UInt] was not reflected in the valid bit logic.
 2023-04-24 14:01:39 -07:00
Hansung Kim
7539c39c45 Store SizeEnum in entry instead of UInt 2023-04-23 22:34:19 -07:00
Richard Yan
5d105b36c5 Merge branch 'richard-dev' into graphics 2023-04-23 21:34:52 -07:00
Richard Yan
a872856263 quick coalescer connection fix 2023-04-23 21:31:25 -07:00
Richard Yan
7663a03a8c coalescer implementation passing compilation 2023-04-23 21:29:07 -07:00
Hansung Kim
c21a196907 scalafmt 2023-04-23 20:56:55 -07:00
Richard Yan
647d7b8628 WIP multi-coalescer 2023-04-23 20:31:54 -07:00
Richard Yan
bac8916ba1 mono coalescer implementation 2023-04-23 15:55:46 -07:00
Hansung Kim
0f2e4ee8aa Store UInt instead of ChiselEnum in entry; pass tests 
Scala isn't happy with storing ChiselEnum type for some reason
 2023-04-23 15:28:12 -07:00
Hansung Kim
8cee61a591 Uncoalesce using table size enum 2023-04-23 14:42:10 -07:00
Hansung Kim
ccf9b95fb5 Create custom response bundle to decouple from TileLink 
... and easier unit testing.
 2023-04-23 13:37:10 -07:00
Hansung Kim
4d16ec9b08 Allow trace driver to make double-word reqs 
This is mostly for testing purposes.
 2023-04-23 12:24:26 -07:00
Hansung Kim
a7baf57e49 Left out fix 2023-04-23 12:09:47 -07:00
Hansung Kim
a71c0aed73 Don't set default filename in class initializers 2023-04-23 12:07:52 -07:00
Hansung Kim
b6115cc394 Fix generating PutPartialData from toTLA 
Including mask in the argument calls the method override that generates
PutPartialData.
 2023-04-23 11:53:42 -07:00
Hansung Kim
0c0a8ec553 SimMemTraceLogger: store handle in class 2023-04-23 11:27:06 -07:00
Richard Yan
a84757f8f8 restructure parameters into config object && cleanup 2023-04-23 03:09:20 -07:00
Richard Yan
d28216182c merge graphics 2023-04-23 00:54:24 -07:00
Richard Yan
684f732a9a it compiles (& coal gen reorg) 2023-04-23 00:41:35 -07:00
Hansung Kim
2a82e8d119 Fix TL data mask stencil logic in MemTraceLogger 2023-04-23 00:39:59 -07:00
Hansung Kim
6cd27faed2 Respect old req size in uncoalescer 2023-04-22 23:04:47 -07:00
Richard Yan
85e3a6a940 somehow merged 2023-04-22 21:56:57 -07:00
Richard Yan
b895d304bb pre-merge 2023-04-22 21:28:38 -07:00
Hansung Kim
90a797e71a Make MemTraceDriver generate word-sized requests 
Try to model the core's behavior which accesses cache in word granularity.  This
also simplifies the coalescer design as coalescer no longer needs to uncoalesce
response data chunk into single bytes (and therefore fewer muxes).
 2023-04-22 21:04:45 -07:00
Hansung Kim
c5d722112b Make word size global object 2023-04-22 14:58:02 -07:00
Hansung Kim
8a7e6f1391 Replace hardcoded trace widths with proper params 2023-04-21 18:20:16 -07:00
Hansung Kim
bbe62a8583 Properly count per-lane req/resps 2023-04-21 17:24:43 -07:00
Hansung Kim
db06bda674 Count req/resp lines and bytes to coalescer and test match 
Note total bytes in requests and responses (i.e. traffic) don't
need to match because of redundant requests to the same address may get
coalesced.
 2023-04-21 16:49:19 -07:00
Hansung Kim
3ba566b9f7 Give slack time after trace EOF before sim termination 
... so that we make sure to receive all outstanding responses.
This fixes the response traces being truncated too early.
 2023-04-21 16:27:20 -07:00
Hansung Kim
3f9f7a1d67 Generate proper AccessAck/AccessAckData from response queue 2023-04-21 16:14:52 -07:00
Hansung Kim
e04ffe2130 Generate separate traces per logger/req/resp 2023-04-21 15:53:15 -07:00
Hansung Kim
6ae08b6541 Add missing sizeWidth to uncoalescer test 2023-04-21 11:24:57 -07:00
Hansung Kim
de478dcca9 Generate both Put/Get for non-coalesced requests 2023-04-20 21:57:40 -07:00
Hansung Kim
a9719d5e36 Split tl*OpcodeIsStore out to global scope 2023-04-20 21:42:56 -07:00
Hansung Kim
de6d6eee1a Fix request shift queue not enqueuing when empty 
The queue was enabling shifting of the registers whenever deq.ready
was 1, even when the queue was empty.  This caused `wen` to disable
writing enq.bits to any of the entries in the queue.  Fixed by setting
`shift` to 0 when queue is empty.
 2023-04-20 21:12:19 -07:00
Hansung Kim
7e405b5355 Re-enable coalescer in TLRAMCoalescerLoggerTest 
Now that the driver and logger are working (kinda).
 2023-04-20 21:11:12 -07:00
Hansung Kim
b2ab45f5e2 Change parameters to spatial-only coalescing 2023-04-20 21:09:19 -07:00
Richard Yan
8715bede37 WIP coalescer restructure 2023-04-19 01:03:30 -07:00
Hansung Kim
322f340657 Manage to make new bugs while doing that 2023-04-18 00:14:33 -07:00
Hansung Kim
65a22b7fcb Use TLMessages constants instead of numbers 2023-04-18 00:09:48 -07:00
Hansung Kim
2ac5ee398a Doc 2023-04-17 21:31:13 -07:00
Hansung Kim
334d05b222 Remove leftover printf 2023-04-17 21:17:23 -07:00
Hansung Kim
02ce969c67 Fix width mismatch for source logger 2023-04-17 18:52:38 -07:00