Store UInt instead of ChiselEnum in entry; pass tests
Scala isn't happy with storing ChiselEnum type for some reason
This commit is contained in:
Hansung Kim
@@ -456,7 +456,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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// but the width of the size enum
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val newEntry = Wire(
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new InflightCoalReqTableEntry(config.NUM_LANES, numPerLaneReqs, sourceWidth, offsetBits,
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config.SizeEnum)
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config.SizeEnum.getWidth)
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)
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println(s"=========== table sourceWidth: ${sourceWidth}")
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// println(s"=========== table sizeEnumBits: ${newEntry.sizeEnumBits}")
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@@ -472,7 +472,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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r.valid := false.B
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r.source := origReqs(i).source
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r.offset := (origReqs(i).address % (1 << config.MAX_SIZE).U) >> config.WORD_WIDTH
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r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size)
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r.sizeEnum := config.SizeEnum.logSizeToEnum(origReqs(i).size).asUInt
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}
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}
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newEntry.lanes(0).reqs(0).valid := true.B
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@@ -601,14 +601,10 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module {
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ioOldReq.valid := false.B
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ioOldReq.bits := DontCare
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when(inflightTable.io.lookup.valid) {
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when(inflightTable.io.lookup.valid && oldReq.valid) {
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ioOldReq.valid := oldReq.valid
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ioOldReq.bits.source := oldReq.source
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// FIXME: this is janky. We can't use config.SizeEnum.enumToLogSize for
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// some reason because type checker complains that config.SizeEnum.Type
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// is different from found.sizeEnumType.type
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// val logSize = config.SizeEnum.enumToLogSize(oldReq.sizeEnum)
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val logSize = found.sizeEnumType.enumToLogSize(oldReq.sizeEnum)
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val logSize = config.SizeEnum.enumToLogSize(config.SizeEnum(oldReq.sizeEnum))
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ioOldReq.bits.size := logSize
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ioOldReq.bits.data :=
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getCoalescedDataChunk(io.coalResp.bits.data, io.coalResp.bits.data.getWidth, oldReq.offset, logSize)
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@@ -626,7 +622,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
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val offsetBits = 4 // FIXME hardcoded
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val sizeBits = 2 // FIXME hardcoded
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val entryT = new InflightCoalReqTableEntry(config.NUM_LANES, config.DEPTH,
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log2Ceil(config.NUM_OLD_IDS), config.MAX_SIZE, config.SizeEnum)
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log2Ceil(config.NUM_OLD_IDS), config.MAX_SIZE, config.SizeEnum.getWidth)
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val entries = config.NUM_NEW_IDS
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val sourceWidth = log2Ceil(config.NUM_OLD_IDS)
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@@ -655,7 +651,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
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r.valid := false.B
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r.source := 0.U
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r.offset := 0.U
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r.sizeEnum := config.SizeEnum.INVALID
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r.sizeEnum := config.SizeEnum.INVALID.asUInt
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}
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}
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}
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@@ -703,14 +699,14 @@ class InflightCoalReqTableEntry(
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val numPerLaneReqs: Int,
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val sourceWidth: Int,
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val offsetBits: Int,
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val sizeEnumType: InFlightTableSizeEnum
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val sizeEnumBits: Int
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) extends Bundle {
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class PerCoreReq extends Bundle {
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val valid = Bool()
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val valid = Bool() // FIXME: delete this
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// FIXME: oldId and newId shares the same width
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val source = UInt(sourceWidth.W)
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val offset = UInt(offsetBits.W)
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val sizeEnum = sizeEnumType()
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val sizeEnum = UInt(sizeEnumBits.W)
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}
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class PerLane extends Bundle {
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val reqs = Vec(numPerLaneReqs, new PerCoreReq)
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@@ -254,6 +254,22 @@ class CoalShiftQueueTest extends AnyFlatSpec with ChiselScalatestTester {
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}
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}
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object testConfig extends CoalescerConfig(
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MAX_SIZE = 4, // maximum coalesced size
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DEPTH = 2, // request window per lane
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WAIT_TIMEOUT = 8, // max cycles to wait before forced fifo dequeue, per lane
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ADDR_WIDTH = 24, // assume <= 32
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DATA_BUS_SIZE = 4, // 2^4=16 bytes, 128 bit bus
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NUM_LANES = 4,
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// WATERMARK = 2, // minimum buffer occupancy to start coalescing
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WORD_SIZE = 4, // 32-bit system
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WORD_WIDTH = 2, // log(WORD_SIZE)
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NUM_OLD_IDS = 16, // num of outstanding requests per lane, from processor
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NUM_NEW_IDS = 4, // num of outstanding coalesced requests
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COAL_SIZES = Seq(3),
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SizeEnum = DefaultInFlightTableSizeEnum
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)
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class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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behavior of "uncoalescer"
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val numLanes = 4
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@@ -265,7 +281,7 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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val numInflightCoalRequests = 4
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it should "work" in {
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test(new UncoalescingUnit(defaultConfig))
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test(new UncoalescingUnit(testConfig))
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// vcs helps with simulation time, but sometimes errors with
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// "mutation occurred during iteration" java error
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// .withAnnotations(Seq(VcsBackendAnnotation))
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@@ -276,19 +292,21 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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c.io.newEntry.lanes(0).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(0).reqs(0).source.poke(1.U)
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c.io.newEntry.lanes(0).reqs(0).offset.poke(1.U)
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c.io.newEntry.lanes(0).reqs(0).size.poke(2.U)
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c.io.newEntry.lanes(0).reqs(0).sizeEnum.poke(1.U) // 1.U is FOUR
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c.io.newEntry.lanes(0).reqs(1).valid.poke(true.B)
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c.io.newEntry.lanes(0).reqs(1).source.poke(2.U)
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c.io.newEntry.lanes(0).reqs(1).offset.poke(1.U)
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c.io.newEntry.lanes(0).reqs(1).size.poke(2.U)
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c.io.newEntry.lanes(0).reqs(1).offset.poke(0.U)
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c.io.newEntry.lanes(0).reqs(1).sizeEnum.poke(1.U)
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c.io.newEntry.lanes(1).reqs(0).valid.poke(false.B)
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c.io.newEntry.lanes(2).reqs(0).valid.poke(true.B)
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c.io.newEntry.lanes(2).reqs(0).source.poke(1.U)
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c.io.newEntry.lanes(2).reqs(0).source.poke(2.U)
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c.io.newEntry.lanes(2).reqs(0).offset.poke(2.U)
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c.io.newEntry.lanes(2).reqs(0).size.poke(1.U)
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c.io.newEntry.lanes(2).reqs(0).sizeEnum.poke(1.U)
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c.io.newEntry.lanes(2).reqs(1).valid.poke(true.B)
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c.io.newEntry.lanes(2).reqs(1).source.poke(2.U)
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c.io.newEntry.lanes(2).reqs(1).offset.poke(0.U)
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c.io.newEntry.lanes(2).reqs(1).size.poke(2.U)
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c.io.newEntry.lanes(2).reqs(1).offset.poke(3.U)
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c.io.newEntry.lanes(2).reqs(1).sizeEnum.poke(1.U)
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c.io.newEntry.lanes(3).reqs(0).valid.poke(false.B)
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c.clock.step()
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@@ -299,6 +317,7 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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c.io.coalResp.valid.poke(true.B)
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c.io.coalResp.bits.source.poke(sourceId)
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val lit = (BigInt(0x0123456789abcdefL) << 64) | BigInt(0x5ca1ab1edeadbeefL)
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// val lit = BigInt(0x0123456789abcdefL)
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c.io.coalResp.bits.data.poke(lit.U)
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// table lookup is combinational at the same cycle
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@@ -307,12 +326,13 @@ class UncoalescingUnitTest extends AnyFlatSpec with ChiselScalatestTester {
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c.io.uncoalResps(2)(0).valid.expect(true.B)
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c.io.uncoalResps(3)(0).valid.expect(false.B)
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c.io.uncoalResps(0)(0).bits.data.expect(0x89abcdefL.U)
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// offset is counting from LSB
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c.io.uncoalResps(0)(0).bits.data.expect(0x5ca1ab1eL.U)
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c.io.uncoalResps(0)(0).bits.source.expect(1.U)
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c.io.uncoalResps(0)(1).bits.data.expect(0x89abcdefL.U)
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c.io.uncoalResps(0)(1).bits.data.expect(0xdeadbeefL.U)
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c.io.uncoalResps(0)(1).bits.source.expect(2.U)
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c.io.uncoalResps(2)(0).bits.data.expect(0x5ca1ab1eL.U)
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c.io.uncoalResps(2)(0).bits.source.expect(1.U)
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c.io.uncoalResps(2)(0).bits.data.expect(0x89abcdefL.U)
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c.io.uncoalResps(2)(0).bits.source.expect(2.U)
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c.io.uncoalResps(2)(1).bits.data.expect(0x01234567L.U)
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c.io.uncoalResps(2)(1).bits.source.expect(2.U)
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}
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