Renames
This commit is contained in:
Hansung Kim
@@ -37,7 +37,7 @@ object DefaultInFlightTableSizeEnum extends InFlightTableSizeEnum {
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case class CoalescerConfig(
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MAX_SIZE: Int, // maximum burst size (64 bytes)
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DEPTH: Int, // request window per lane
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QUEUE_DEPTH: Int, // request window per lane
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WAIT_TIMEOUT: Int, // max cycles to wait before forced fifo dequeue, per lane
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ADDR_WIDTH: Int, // assume <= 32
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DATA_BUS_SIZE: Int, // 2^4=16 bytes, 128 bit bus
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@@ -54,7 +54,7 @@ case class CoalescerConfig(
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object defaultConfig extends CoalescerConfig(
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// TODO: bigger size
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MAX_SIZE = 3, // maximum burst size (64 bytes)
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DEPTH = 1, // request window per lane
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QUEUE_DEPTH = 1, // request window per lane
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WAIT_TIMEOUT = 8, // max cycles to wait before forced fifo dequeue, per lane
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ADDR_WIDTH = 24, // assume <= 32
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DATA_BUS_SIZE = 3, // 2^3=8 bytes, 64 bit bus
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@@ -247,8 +247,8 @@ class MonoCoalescer(coalSize: Int, windowT: CoalShiftQueue[ReqQueueEntry],
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val results = Output(new Bundle {
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val leaderIdx = Output(UInt(log2Ceil(config.NUM_LANES).W))
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val baseAddr = Output(UInt(config.ADDR_WIDTH.W))
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val matchOH = Output(Vec(config.NUM_LANES, UInt(config.DEPTH.W)))
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val matchCount = Output(UInt(log2Ceil(config.NUM_LANES * config.DEPTH).W))
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val matchOH = Output(Vec(config.NUM_LANES, UInt(config.QUEUE_DEPTH.W)))
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val matchCount = Output(UInt(log2Ceil(config.NUM_LANES * config.QUEUE_DEPTH).W))
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val coverageHits = Output(UInt((1 << config.MAX_SIZE).W))
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})
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})
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@@ -330,8 +330,8 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
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val io = IO(new Bundle {
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val window = Input(Vec(config.NUM_LANES, windowT.io.cloneType))
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val out_req = DecoupledIO(coalReqT.cloneType)
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val invalidate = Output(Valid(Vec(config.NUM_LANES, UInt(config.DEPTH.W))))
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val outReq = DecoupledIO(coalReqT.cloneType)
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val invalidate = Output(Valid(Vec(config.NUM_LANES, UInt(config.QUEUE_DEPTH.W))))
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})
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val coalescers = config.COAL_SIZES.map(size => Module(new MonoCoalescer(size, windowT, config)))
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@@ -407,18 +407,18 @@ class MultiCoalescer(windowT: CoalShiftQueue[ReqQueueEntry], coalReqT: ReqQueueE
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}
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val sourceGen = Module(new ReqSourceGen(log2Ceil(config.NUM_NEW_IDS)))
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sourceGen.io.gen := io.out_req.fire // use up a source ID only when request is created
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sourceGen.io.gen := io.outReq.fire // use up a source ID only when request is created
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io.out_req.bits.source := sourceGen.io.id.bits
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io.out_req.bits.mask := mask.asUInt
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io.out_req.bits.data := data.asUInt
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io.out_req.bits.size := chosenSize
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io.out_req.bits.address := chosenBundle.baseAddr
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io.out_req.bits.op := VecInit(io.window.map(_.elts.head))(chosenBundle.leaderIdx).op
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io.out_req.valid := chosenValid && sourceGen.io.id.valid
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io.outReq.bits.source := sourceGen.io.id.bits
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io.outReq.bits.mask := mask.asUInt
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io.outReq.bits.data := data.asUInt
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io.outReq.bits.size := chosenSize
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io.outReq.bits.address := chosenBundle.baseAddr
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io.outReq.bits.op := VecInit(io.window.map(_.elts.head))(chosenBundle.leaderIdx).op
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io.outReq.valid := chosenValid && sourceGen.io.id.valid
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io.invalidate.bits := chosenBundle.matchOH
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io.invalidate.valid := io.out_req.fire // invalidate only when fire
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io.invalidate.valid := io.outReq.fire // invalidate only when fire
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}
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class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends LazyModuleImp(outer) {
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@@ -434,7 +434,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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// note we are using word size. assuming all coalescer inputs are word sized
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val reqQueueEntryT = new ReqQueueEntry(sourceWidth, config.WORD_WIDTH, config.ADDR_WIDTH, config.WORD_SIZE)
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val reqQueues = Seq.tabulate(config.NUM_LANES) { _ =>
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Module(new CoalShiftQueue(reqQueueEntryT, config.DEPTH))
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Module(new CoalShiftQueue(reqQueueEntryT, config.QUEUE_DEPTH))
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}
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val coalReqT = new ReqQueueEntry(sourceWidth, log2Ceil(config.MAX_SIZE), config.ADDR_WIDTH, config.MAX_SIZE)
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@@ -488,9 +488,9 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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val (tlCoal, edgeCoal) = outer.coalescerNode.out(0)
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tlCoal.a.valid := coalescer.io.out_req.valid
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tlCoal.a.bits := coalescer.io.out_req.bits.toTLA(edgeCoal)
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coalescer.io.out_req.ready := tlCoal.a.ready
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tlCoal.a.valid := coalescer.io.outReq.valid
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tlCoal.a.bits := coalescer.io.outReq.bits.toTLA(edgeCoal)
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coalescer.io.outReq.ready := tlCoal.a.ready
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tlCoal.b.ready := true.B
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tlCoal.c.valid := false.B
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// tlCoal.d.ready := true.B // this should be connected to uncoalescer's ready, done below.
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@@ -505,7 +505,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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// The maximum number of requests from a single lane that can go into a
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// coalesced request. Upper bound is min(DEPTH, 2**sourceWidth).
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val numPerLaneReqs = config.DEPTH
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val numPerLaneReqs = config.QUEUE_DEPTH
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val respQueueEntryT = new RespQueueEntry(sourceWidth, log2Ceil(config.MAX_SIZE), config.MAX_SIZE)
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val respQueues = Seq.tabulate(config.NUM_LANES) { _ =>
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@@ -624,7 +624,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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)
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println(s"=========== table sourceWidth: ${sourceWidth}")
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// println(s"=========== table sizeEnumBits: ${newEntry.sizeEnumBits}")
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newEntry.source := coalescer.io.out_req.bits.source
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newEntry.source := coalescer.io.outReq.bits.source
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// TODO: richard to write table fill logic
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// FIXME: this assertion used to say 1 << config.MAX_SIZE
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@@ -655,7 +655,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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// Uncoalescer module uncoalesces responses back to each lane
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val uncoalescer = Module(new UncoalescingUnit(config))
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uncoalescer.io.coalReqValid := coalescer.io.out_req.valid
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uncoalescer.io.coalReqValid := coalescer.io.outReq.valid
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uncoalescer.io.newEntry := newEntry
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// Cleanup: custom <>?
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uncoalescer.io.coalResp.valid := tlCoal.d.valid
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@@ -679,7 +679,7 @@ class CoalescingUnitImp(outer: CoalescingUnit, config: CoalescerConfig) extends
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}
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// Debug
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dontTouch(coalescer.io.out_req)
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dontTouch(coalescer.io.outReq)
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val coalRespData = tlCoal.d.bits.data
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dontTouch(coalRespData)
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@@ -717,7 +717,7 @@ class UncoalescingUnit(config: CoalescerConfig) extends Module {
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Vec(
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config.NUM_LANES,
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Vec(
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config.DEPTH,
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config.QUEUE_DEPTH,
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ValidIO(
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new RespQueueEntry(log2Ceil(config.NUM_OLD_IDS), config.WORD_WIDTH, config.WORD_SIZE)
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)
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@@ -803,7 +803,7 @@ class InflightCoalReqTable(config: CoalescerConfig) extends Module {
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val sizeBits = 2 // FIXME hardcoded
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val entryT = new InflightCoalReqTableEntry(
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config.NUM_LANES,
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config.DEPTH,
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config.QUEUE_DEPTH,
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log2Ceil(config.NUM_OLD_IDS),
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config.MAX_SIZE,
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config.SizeEnum
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