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Commit Graph

98 Commits

Author SHA1 Message Date
Jerry Zhao
bca38967f8 Merge remote-tracking branch 'origin/master' into mask_penalty 2021-02-22 01:35:08 -08:00
Jerry Zhao
ddea19825d Macrocompiler should prioritize memories with no masks with DefaultCostMetric 2021-02-22 01:30:47 -08:00
chick
ca4013b830 Remove deprecated Driver stuff macros package 
- Fix name reference and weird .get.get in CostMetric
- Update to DependencyAPIMigration
  - MacroCompilerTransform
  - MacroCompilerOptimizations
- Delete unused class MacroCompiler
- Remove use of ExecutionOptionsManager in object MacroCompiler
- Removed stack trace when no arguments from CLI, just give message requiring args
- Update version to 0.4-SNAPSHOT
 2021-02-08 09:09:19 -08:00
chick
d9d9d0fbb5 Move to scalatest 3.2 
Requires updating to AnyFlatSpec where used
And different import for Matchers
 2021-02-03 21:03:22 -08:00
chick
68c3425493 Reformat all scala files in macros 
- Mostly this reformat comments and large argument lists to classes and methods
 2021-02-03 17:50:36 -08:00
chick
19e51f3df5 Make the directory structure match the packages 
All tests run as they did prior to the changes
 2021-02-03 17:46:12 -08:00
Tim Snyder
20d370be49 Merge branch 'firrtl-1.4-remove-clk-stuff' into chisel34 2020-10-23 13:08:48 -05:00
Tim Snyder
446cb84cbf fixup! Update MacroCompiler for Chisel 3.4 
Need to collect the annotations into a Seq.
Also updated the macros project tests.
 2020-10-23 18:02:42 +00:00
Tim Snyder
fc3a3eabff Update MacroCompiler for Chisel 3.4 2020-10-21 21:08:51 +00:00
chick
8903c04c2d - fix call to ceilLog2 in macros 2020-09-29 10:59:48 -07:00
chick
e4cd2b01fe This is mess clean it up 2020-09-10 14:35:10 -07:00
Albert Magyar
c4e5f66c5e Provide MidForm circuit to MacroCompilerTransform 2020-05-13 10:34:57 -07:00
Albert Magyar
757c39ac1c Change macrocompiler to support FIRRTL 1.3 -- not backwards compatible 2020-05-13 10:34:57 -07:00
Colin Schmidt
5fcae01825 Fix width of zeros after #74 2020-02-19 18:52:48 -08:00
Colin Schmidt
a00771d33a Merge branch 'master' into bump_chisel_3.2.x 2020-02-19 18:05:16 -08:00
Colin Schmidt
db0efd38fc Fix CI tests 2020-02-19 17:23:10 -08:00
Albert Magyar
8ca876503c Correctly specify width of default zero output value (#74) 2020-02-11 20:04:22 -07:00
Abraham Gonzalez
ecc52b9b7c add test case for we bug 2019-11-05 21:29:57 -08:00
Abraham Gonzalez
34984802b2 enforce re is disabled when we is enabled 2019-11-05 14:16:53 -08:00
Abraham Gonzalez
46e2ecb9ae Fix MacroCompiler for CE-less Library Memories 
If a memory doesn't have a mask and doesn't have a chip enable, make sure that you use the `mem` chip enable to connect to the `we` port on the `lib` memory. Fixes a bug where the `lib` `we` signal would be tied to the `mem` `wmode` signal but then the macro would have no `en` signal connected to it.
 2019-11-05 14:04:31 -08:00
Abraham Gonzalez
6c59cac744 fix spacing 2019-10-28 13:47:07 -07:00
Abraham Gonzalez
be3b05a909 add test case 2019-10-28 13:45:05 -07:00
Abraham Gonzalez
7f0828cb30 Fix macrocompiler for RW mask port 2019-10-25 20:42:55 -07:00
John Wright
82636b3ff4 Upstream MemConf and use it (with some slight tweaks) 2019-05-14 10:10:47 -07:00
Colin Schmidt
c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
Colin Schmidt
affd033f0a Emit hammer IR from MacroCompiler (#50) 2019-03-25 22:52:39 -07:00
Abraham Gonzalez
817726ff1f stop exceptions on empty conf files (#43) 
* stop exceptions on empty conf files

* emit empty verilog file | warn users

* put else's on same line as closing bracket
 2019-03-18 10:15:50 -07:00
Colin Schmidt
0b9d74ada7 Fix unit tests update cost function once more 
bump mdf to master
 2019-03-18 07:25:04 -07:00
Colin Schmidt
44e97826d4 Fix cost metric for non Compiler libs 
Also a small fix from reviewer
 2019-03-18 07:25:04 -07:00
Colin Schmidt
98a410812c Filter compiler libraries before mapping 
The filter is always by family and maskability and then by any
integral mappings.
 2019-03-18 07:25:04 -07:00
Colin Schmidt
a0510e6664 Change cost to double from BigInt and fix default metric 
I don't think it was adding anything and now we can get rid of
the weird +1/-1
 2019-03-18 07:25:04 -07:00
Colin Schmidt
45278a6de0 Make SRAM per port clocks optional 
Connects to whatever clock ports are available
 2019-03-18 07:25:04 -07:00
James Dunn
9d505d6063 Fixed index offset in mask port mapping. (#38) 
Fixed index offset in mask port mapping.
 2019-02-13 15:17:12 -08:00
John Wright
1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00
John Wright
efd2f09b21 Naming consistency (memMode -> memFormat) 2019-02-13 10:15:51 -08:00
John Wright
f0c7bab3ea Use the correct 'magic values' for the port names 
Ensure backwards compatiblity by using -m for MDF input and -n for conf
input. Also fix the naming scheme for memory ports.
 2019-02-13 10:15:51 -08:00
John Wright
d861fdd95c Don't run DCE && Profit 2019-02-13 10:15:51 -08:00
John Wright
12842cb3a7 Add MemConf and change MacroCompiler to use a conf file instead of MDF JSON 2019-02-13 10:15:51 -08:00
Paul Rigge
f310d45381 Refactor barstools for new versions of things. 
- No handlebars (not being published for Scala 2.12)
- Update for new annotations APIs

Bump sbt-dependency-graph to 0.9.2 for this scala version
 2019-02-13 10:15:51 -08:00
Edward Wang
4727d475c7 Add options to force certain memories to lib or synflops 2019-02-06 12:40:53 -08:00
Edward Wang
d1c1b3fba6 Overhaul CompilerMode parsing 2019-02-06 12:40:53 -08:00
edwardcwang
93bf7895be Fix corner case in compiling a small mem using a large lib (#32) 
* Refactor bit pairs calculation into a separate function

* Minor clarifications

* Clarify MacroCompilerSpec helpers

* Add SmallTagArrayTest test

* Fix corner case in compiling a small mem using a large lib
 2018-04-26 10:33:55 -07:00
Adam Izraelevitz
79c8c283cc Add memory compiler to macros (#29) 
* Add memory compiler to macros

* Removed weird spacing

* Make sramcompiler width/depth range inclusive

* Added sramcompiler test
 2018-02-16 16:01:10 -08:00
edwardcwang
8a30579a3e Support firrtl output in command line for MacroCompiler (#28) 
* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
 2017-12-04 15:12:42 -08:00
edwardcwang
c884a2fb15 Correct multi-ported memory compilation (#27) 
* Correct multi-ported memory compilation

It was incorrectly splitting multiple times before. Fixed the issue and
added regression tests for this issue.

* Add 1 read 1 write test
 2017-10-06 18:04:49 -07:00
Edward Wang
e1499fcdc0 Update command line help 2017-10-03 11:56:30 -07:00
Edward Wang
e09f8b1b0d Fix grammar 2017-10-03 11:56:30 -07:00
Edward Wang
bc26f5eb1a Address review comments 2017-10-03 11:56:30 -07:00
Edward Wang
d2b105079d Not a scaladoc 2017-10-03 11:56:30 -07:00
Edward Wang
13d8a0f8f5 Add strict mode 2017-10-03 11:56:30 -07:00