This is mess clean it up
This commit is contained in:
chick
26
.scalafmt.conf
Normal file
26
.scalafmt.conf
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@@ -0,0 +1,26 @@
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version = 2.6.4
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maxColumn = 120
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align = most
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continuationIndent.defnSite = 2
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assumeStandardLibraryStripMargin = true
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docstrings = ScalaDoc
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lineEndings = preserve
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includeCurlyBraceInSelectChains = false
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danglingParentheses = true
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align.tokens.add = [
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{
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code = ":"
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}
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]
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newlines.alwaysBeforeCurlyBraceLambdaParams = false
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newlines.alwaysBeforeMultilineDef = false
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newlines.implicitParamListModifierForce = [before]
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verticalMultiline.atDefnSite = true
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optIn.annotationNewlines = true
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rewrite.rules = [SortImports, PreferCurlyFors, AvoidInfix]
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@@ -1,8 +1,8 @@
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// See LICENSE for license details.
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val defaultVersions = Map(
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"chisel3" -> "3.2-SNAPSHOT",
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"chisel-iotesters" -> "1.3-SNAPSHOT"
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"chisel3" -> "3.4-SNAPSHOT",
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"chisel-iotesters" -> "1.5-SNAPSHOT"
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)
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lazy val commonSettings = Seq(
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@@ -1,9 +1,10 @@
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// See LICENSE for license details.
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package barstools.macros
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import firrtl.ir.{Circuit, NoInfo}
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import firrtl.passes.RemoveEmpty
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import firrtl.Parser.parse
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import firrtl.Utils.ceilLog2
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import java.io.{File, StringWriter}
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import mdf.macrolib.SRAMMacro
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@@ -1,247 +0,0 @@
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package barstools.tapeout.transforms.clkgen
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import net.jcazevedo.moultingyaml._
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import firrtl.annotations._
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import chisel3.experimental._
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import chisel3._
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import firrtl._
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import firrtl.transforms.DedupModules
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object ClkAnnotationsYaml extends DefaultYamlProtocol {
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implicit val _clksrc = yamlFormat3(ClkSrc)
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implicit val _sink = yamlFormat1(Sink)
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implicit val _clkport = yamlFormat2(ClkPortAnnotation)
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implicit val _genclk = yamlFormat4(GeneratedClk)
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implicit val _clkmod = yamlFormat2(ClkModAnnotation)
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}
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case class ClkSrc(period: Double, waveform: Seq[Double] = Seq(), async: Seq[String] = Seq()) {
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def getWaveform = if (waveform == Seq.empty) Seq(0, period/2) else waveform
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// async = ids of top level clocks that are async with this clk
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// Default is 50% duty cycle, period units is default
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require(getWaveform.sorted == getWaveform, "Waveform edges must be in order")
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require(getWaveform.length == 2, "Must specify time for rising edge, then time for falling edge")
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}
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case class Sink(src: Option[ClkSrc] = None)
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case class ClkPortAnnotation(tag: Option[Sink] = None, id: String) {
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import ClkAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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}
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abstract class ClkModType {
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def serialize: String
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}
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case object ClkMux extends ClkModType {
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def serialize: String = "mux"
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}
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case object ClkDiv extends ClkModType {
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def serialize: String = "div"
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}
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case object ClkGen extends ClkModType {
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def serialize: String = "gen"
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}
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// Unlike typical SDC, starts at 0.
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// Otherwise, see pg. 63 of "Constraining Designs for Synthesis and Timing Analysis"
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// by S. Gangadharan
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// original clk: |-----|_____|-----|_____|
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// edges: 0 1 2 3 4
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// div. by 4, 50% duty cycle --> edges = 0, 2, 4
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// ---> |-----------|___________|
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// sources = source id's
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case class GeneratedClk(
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id: String,
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sources: Seq[String] = Seq(),
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referenceEdges: Seq[Int] = Seq(),
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period: Option[Double] = None) {
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require(referenceEdges.sorted == referenceEdges, "Edges must be in order for generated clk")
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if (referenceEdges.nonEmpty) require(referenceEdges.length % 2 == 1, "# of reference edges must be odd!")
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}
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case class ClkModAnnotation(tpe: String, generatedClks: Seq[GeneratedClk]) {
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def modType: ClkModType = HasClkAnnotation.modType(tpe)
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modType match {
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case ClkDiv =>
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generatedClks foreach { c =>
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require(c.referenceEdges.nonEmpty, "Reference edges must be defined for clk divider!")
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require(c.sources.length == 1, "Clk divider output can only have 1 source")
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require(c.period.isEmpty, "No period should be specified for clk divider output")
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}
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case ClkMux =>
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generatedClks foreach { c =>
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require(c.referenceEdges.isEmpty, "Reference edges must not be defined for clk mux!")
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require(c.period.isEmpty, "No period should be specified for clk mux output")
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require(c.sources.nonEmpty, "Clk muxes must have sources!")
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}
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case ClkGen =>
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generatedClks foreach { c =>
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require(c.referenceEdges.isEmpty, "Reference edges must not be defined for clk gen!")
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require(c.sources.isEmpty, "Clk generators shouldn't have constrained sources")
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require(c.period.nonEmpty, "Clk generator output period should be specified!")
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}
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}
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import ClkAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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}
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abstract class FirrtlClkTransformAnnotation {
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def targetName: String
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}
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// Firrtl version
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case class TargetClkModAnnoF(target: ModuleName, anno: ClkModAnnotation) extends FirrtlClkTransformAnnotation with SingleTargetAnnotation[ModuleName] {
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def duplicate(n: ModuleName): TargetClkModAnnoF = this.copy(target = n)
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def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize)
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def targetName = target.name
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def modType = anno.modType
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def generatedClks = anno.generatedClks
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def getAllClkPorts = anno.generatedClks.map(x =>
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List(List(x.id), x.sources).flatten).flatten.distinct.map(Seq(targetName, _).mkString("."))
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}
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// Chisel version
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case class TargetClkModAnnoC(target: Module, anno: ClkModAnnotation) extends ChiselAnnotation {
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def toFirrtl = TargetClkModAnnoF(target.toNamed, anno)
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}
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// Firrtl version
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case class TargetClkPortAnnoF(target: ComponentName, anno: ClkPortAnnotation) extends FirrtlClkTransformAnnotation with SingleTargetAnnotation[ComponentName] {
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def duplicate(n: ComponentName): TargetClkPortAnnoF = this.copy(target = n)
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def getAnno = Annotation(target, classOf[ClkSrcTransform], anno.serialize)
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def targetName = Seq(target.module.name, target.name).mkString(".")
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def modId = Seq(target.module.name, anno.id).mkString(".")
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def sink = anno.tag
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}
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// Chisel version
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case class TargetClkPortAnnoC(target: Element, anno: ClkPortAnnotation) extends ChiselAnnotation {
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def toFirrtl = TargetClkPortAnnoF(target.toNamed, anno)
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}
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object HasClkAnnotation {
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import ClkAnnotationsYaml._
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def modType(tpe: String): ClkModType = tpe match {
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case s: String if s == ClkMux.serialize => ClkMux
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case s: String if s == ClkDiv.serialize => ClkDiv
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case s: String if s == ClkGen.serialize => ClkGen
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case _ => throw new Exception("Clock module annotaiton type invalid")
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}
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def unapply(a: Annotation): Option[FirrtlClkTransformAnnotation] = a match {
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case Annotation(f, t, s) if t == classOf[ClkSrcTransform] => f match {
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case m: ModuleName =>
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Some(TargetClkModAnnoF(m, s.parseYaml.convertTo[ClkModAnnotation]))
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case c: ComponentName =>
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Some(TargetClkPortAnnoF(c, s.parseYaml.convertTo[ClkPortAnnotation]))
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case _ => throw new Exception("Clk source annotation only valid on module or component!")
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}
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case _ => None
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}
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def apply(annos: Seq[Annotation]): Option[(Seq[TargetClkModAnnoF],Seq[TargetClkPortAnnoF])] = {
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// Get all clk-related annotations
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val clkAnnos = annos.map(x => unapply(x)).flatten
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val targets = clkAnnos.map(x => x.targetName)
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require(targets.distinct.length == targets.length, "Only 1 clk related annotation is allowed per component/module")
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if (clkAnnos.length == 0) None
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else {
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val componentAnnos = clkAnnos.filter {
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case TargetClkPortAnnoF(ComponentName(_, ModuleName(_, _)), _) => true
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case _ => false
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}.map(x => x.asInstanceOf[TargetClkPortAnnoF])
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val associatedMods = componentAnnos.map(x => x.target.module.name)
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val moduleAnnos = clkAnnos.filter {
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case TargetClkModAnnoF(ModuleName(m, _), _) =>
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require(associatedMods contains m, "Clk modules should always have clk port annotations!")
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true
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case _ => false
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}.map(x => x.asInstanceOf[TargetClkModAnnoF])
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Some((moduleAnnos, componentAnnos))
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}
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}
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}
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// Applies to both black box + normal module
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trait IsClkModule {
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self: chisel3.Module =>
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doNotDedup(this)
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private def extractElementNames(signal: Data): Seq[String] = {
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val names = signal match {
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case elt: Record =>
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elt.elements.map { case (key, value) => extractElementNames(value).map(x => key + "_" + x) }.toSeq.flatten
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case elt: Vec[_] =>
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elt.zipWithIndex.map { case (elt, i) => extractElementNames(elt).map(x => i + "_" + x) }.toSeq.flatten
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case elt: Element => Seq("")
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case elt => throw new Exception(s"Cannot extractElementNames for type ${elt.getClass}")
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}
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names.map(s => s.stripSuffix("_"))
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}
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// TODO: Replace!
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def extractElements(signal: Data): Seq[Element] = {
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signal match {
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case elt: Record =>
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elt.elements.map { case (key, value) => extractElements(value) }.toSeq.flatten
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case elt: Vec[_] =>
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elt.map { elt => extractElements(elt) }.toSeq.flatten
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case elt: Element => Seq(elt)
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case elt => throw new Exception(s"Cannot extractElements for type ${elt.getClass}")
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}
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}
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def getIOName(signal: Element): String = {
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val possibleNames = extractElements(io).zip(extractElementNames(io)).map {
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case (sig, name) if sig == signal => Some(name)
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case _ => None
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}.flatten
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if (possibleNames.length == 1) possibleNames.head
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else throw new Exception("You can only get the name of an io port!")
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}
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def annotateDerivedClks(tpe: ClkModType, generatedClks: Seq[GeneratedClk]): Unit =
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annotateDerivedClks(ClkModAnnotation(tpe.serialize, generatedClks))
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def annotateDerivedClks(anno: ClkModAnnotation): Unit = annotateDerivedClks(this, anno)
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def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit =
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annotate(TargetClkModAnnoC(m, anno))
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def annotateClkPort(p: Element): Unit = annotateClkPort(p, None, "")
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def annotateClkPort(p: Element, sink: Sink): Unit = annotateClkPort(p, Some(sink), "")
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def annotateClkPort(p: Element, id: String): Unit = annotateClkPort(p, None, id)
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def annotateClkPort(p: Element, sink: Sink, id: String): Unit = annotateClkPort(p, Some(sink), id)
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def annotateClkPort(p: Element, sink: Option[Sink], id: String): Unit = {
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// If no id is specified, it'll try to figure out a name, assuming p is an io port
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val newId = id match {
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case "" =>
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getIOName(p)
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case _ => id
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}
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annotateClkPort(p, ClkPortAnnotation(sink, newId))
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}
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def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = {
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DataMirror.directionOf(p) match {
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case chisel3.core.ActualDirection.Input =>
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require(anno.tag.nonEmpty, "Module inputs must be clk sinks")
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require(anno.tag.get.src.isEmpty,
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"Clock module (not top) input clks should not have clk period, etc. specified")
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case chisel3.core.ActualDirection.Output =>
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require(anno.tag.isEmpty, "Module outputs must not be clk sinks (they're sources!)")
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case _ =>
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throw new Exception("Clk port direction must be specified!")
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}
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p match {
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case _: chisel3.core.Clock =>
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case _ => throw new Exception("Clock port must be of type Clock")
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}
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annotate(TargetClkPortAnnoC(p, anno))
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}
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}
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@@ -1,130 +0,0 @@
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package barstools.tapeout.transforms.clkgen
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import chisel3.experimental.{withClockAndReset, withClock, withReset}
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import chisel3._
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import barstools.tapeout.transforms._
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import chisel3.util.HasBlackBoxInline
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// WARNING: ONLY WORKS WITH VERILATOR B/C YOU NEED ASYNC RESET!
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class SEClkDividerIO(phases: Seq[Int]) extends Bundle {
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val reset = Input(Bool())
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val inClk = Input(Clock())
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val outClks = Output(CustomIndexedBundle(Clock(), phases))
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override def cloneType = (new SEClkDividerIO(phases)).asInstanceOf[this.type]
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}
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class SEClkDividerBB(phases: Seq[Int], f: String) extends BlackBox with HasBlackBoxInline {
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val verilog = scala.io.Source.fromFile(f).getLines.mkString("\n")
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// names without io
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val io = IO(new SEClkDividerIO(phases))
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val modName = this.getClass.getSimpleName
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require(verilog contains modName, "Clk divider Verilog module must be named ClkDividerBB")
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io.elements foreach { case (field, elt) =>
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require(verilog contains field, s"Verilog file should contain io ${field}")}
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setInline(s"${modName}.v", verilog)
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}
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class AsyncRegInit extends BlackBox with HasBlackBoxInline {
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val io = IO(new Bundle {
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val clk = Input(Clock())
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val reset = Input(Bool())
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val init = Input(Bool())
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val in = Input(Bool())
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val out = Output(Bool())
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})
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setInline("AsyncRegInit.v",
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s"""
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|module AsyncRegInit(
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| input clk,
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| input reset,
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| input init,
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| input in,
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| output reg out
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|);
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| always @ (posedge clk or posedge reset) begin
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| if (reset) begin
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| out <= init;
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| end else begin
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| out <= in;
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| end
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| end
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|endmodule
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""".stripMargin)
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}
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object AsyncRegInit {
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def apply(clk: Clock, reset: Bool, init: Bool): AsyncRegInit = {
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val asyncRegInit = Module(new AsyncRegInit)
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asyncRegInit.io.clk := clk
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asyncRegInit.io.reset := reset
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asyncRegInit.io.init := init
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asyncRegInit
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}
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}
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// TODO: Convert analogFile into implicit?
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// If syncReset = false, it's implied that reset is strobed before any clk rising edge happens
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// i.e. when this is a clkgen fed by another clkgen --> need to adjust the indexing b/c
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// you're already shifting on the first clk rising edge
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class SEClkDivider(divBy: Int, phases: Seq[Int], analogFile: String = "", syncReset: Boolean = true)
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extends Module with IsClkModule {
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require(phases.distinct.length == phases.length, "Phases should be distinct!")
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phases foreach { p =>
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require(p < divBy, "Phases must be < divBy")
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}
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val io = IO(new SEClkDividerIO(phases))
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annotateClkPort(io.inClk, Sink())
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val referenceEdges = phases.map(p => Seq(2 * p, 2 * (p + 1), 2 * (p + divBy)))
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val generatedClks = io.outClks.elements.zip(referenceEdges).map { case ((field, eltx), edges) =>
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val elt = eltx.asInstanceOf[Element]
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annotateClkPort(elt)
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GeneratedClk(getIOName(elt), sources = Seq(getIOName(io.inClk)), edges)
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}.toSeq
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annotateDerivedClks(ClkDiv, generatedClks)
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require(divBy >= 1, "Clk division factor must be >= 1")
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divBy match {
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case i: Int if i == 1 =>
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require(phases == Seq(0), "Clk division by 1 shouldn't generate new phases")
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io.outClks(0) := io.inClk
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case i: Int if i > 1 && analogFile == "" =>
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// Shift register based clock divider (duty cycle is NOT 50%)
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val initVals = Seq(true.B) ++ Seq.fill(divBy - 1)(false.B)
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/************ Real design assumes asnyc reset!!!
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withClockAndReset(io.inClk, io.reset) {
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val regs = initVals.map(i => RegInit(i))
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// Close the loop
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regs.head := regs.last
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// Shift register
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regs.tail.zip(regs.init) foreach { case (lhs, rhs) => lhs := rhs }
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// Assign register output to correct clk out
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phases foreach { idx => io.outClks(idx) := regs(idx).asClock }
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}
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*************/
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val regs = initVals.map(i => AsyncRegInit(io.inClk, io.reset, i))
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regs.head.io.in := regs.last.io.out
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regs.tail.zip(regs.init) foreach { case (lhs, rhs) => lhs.io.in := rhs.io.out }
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phases foreach { idx =>
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val regIdx = if (syncReset) idx else (idx + 1) % divBy
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io.outClks(idx) := regs(regIdx).io.out.asClock
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}
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case _ =>
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if (new java.io.File(analogFile).exists) {
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val bb = Module(new SEClkDividerBB(phases, analogFile))
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io <> bb.io
|
||||
}
|
||||
else throw new Exception("Clock divider Verilog file invalid!")
|
||||
}
|
||||
}
|
||||
@@ -1,34 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package barstools.tapeout.transforms.clkgen
|
||||
|
||||
import firrtl._
|
||||
import firrtl.passes._
|
||||
|
||||
import scala.collection.mutable
|
||||
|
||||
class ClkSrcTransform extends Transform with SeqTransformBased {
|
||||
|
||||
override def inputForm: CircuitForm = LowForm
|
||||
override def outputForm: CircuitForm = LowForm
|
||||
|
||||
val transformList = new mutable.ArrayBuffer[Transform]
|
||||
def transforms = transformList
|
||||
|
||||
override def execute(state: CircuitState): CircuitState = {
|
||||
val collectedAnnos = HasClkAnnotation(getMyAnnotations(state))
|
||||
collectedAnnos match {
|
||||
// Transform not used
|
||||
case None => CircuitState(state.circuit, LowForm)
|
||||
case Some((clkModAnnos, clkPortAnnos)) =>
|
||||
val targetDir = barstools.tapeout.transforms.GetTargetDir(state)
|
||||
|
||||
transformList ++= Seq(
|
||||
// InferTypes,
|
||||
new CreateClkConstraints(clkModAnnos, clkPortAnnos, targetDir)
|
||||
)
|
||||
val ret = runTransforms(state)
|
||||
CircuitState(ret.circuit, outputForm, ret.annotations, ret.renames)
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1,152 +0,0 @@
|
||||
// See license file for details
|
||||
|
||||
package barstools.tapeout.transforms.clkgen
|
||||
|
||||
import firrtl.passes.clocklist._
|
||||
import firrtl.annotations._
|
||||
import firrtl.ir._
|
||||
import firrtl.Utils._
|
||||
import barstools.tapeout.transforms._
|
||||
import scala.collection.immutable.ListMap
|
||||
|
||||
// TODO: Really should be moved out of memlib
|
||||
import firrtl.passes.memlib.AnalysisUtils._
|
||||
import firrtl.passes._
|
||||
|
||||
// TODO: Wait until Albert merges into firrtl
|
||||
import firrtl.analyses._
|
||||
|
||||
class CreateClkConstraints(
|
||||
clkModAnnos: Seq[TargetClkModAnnoF],
|
||||
clkPortAnnos: Seq[TargetClkPortAnnoF],
|
||||
targetDir: String) extends Pass {
|
||||
|
||||
// TODO: Are annotations only valid on ports?
|
||||
|
||||
def run(c: Circuit): Circuit = {
|
||||
/*
|
||||
val top = c.main
|
||||
|
||||
// Remove everything from the circuit, unless it has a clock type
|
||||
// This simplifies the circuit drastically so InlineInstances doesn't take forever.
|
||||
val onlyClockCircuit = RemoveAllButClocks.run(c)
|
||||
|
||||
val instanceGraph = new InstanceGraph(onlyClockCircuit)
|
||||
|
||||
val clkModNames = clkModAnnos.map(x => x.targetName)
|
||||
// ** Module name -> Absolute path of (unique) instance
|
||||
val clkMods = clkModNames.map { x =>
|
||||
// NoDeDup was run so only 1 instance of each module should exist
|
||||
val inst = instanceGraph.findInstancesInHierarchy(x)
|
||||
require(inst.length == 1, "Clk modules should have not ben dedup-ed")
|
||||
// Return map of module name to absolute path as a string
|
||||
// Note: absolute path doesn't contain top module + to work with inlineInstances,
|
||||
// delimit with $
|
||||
x -> inst.head.tail.map(y => y.name).mkString("$")
|
||||
}.toMap
|
||||
|
||||
val clkPortIds = clkPortAnnos.map { a => a.modId }
|
||||
require(clkPortIds.distinct.length == clkPortIds.length, "All clk port IDs must be unique!")
|
||||
|
||||
val allModClkPorts = clkModAnnos.map { x =>
|
||||
val modClkPorts = x.getAllClkPorts
|
||||
require(modClkPorts.intersect(clkPortIds).length == modClkPorts.length,
|
||||
"Clks given relationships via clk modules must have been annotated as clk ports")
|
||||
modClkPorts
|
||||
}.flatten.distinct
|
||||
|
||||
val clkPortMap = clkPortIds.zip(clkPortAnnos).toMap
|
||||
val clkModMap = clkModNames.zip(clkModAnnos).toMap
|
||||
|
||||
val (clkSinksTemp, clkSrcsTemp) = clkPortAnnos.partition {
|
||||
case TargetClkPortAnnoF(_, ClkPortAnnotation(tag, _)) if tag.nonEmpty => true
|
||||
case _ => false
|
||||
}
|
||||
|
||||
def convertClkPortAnnoToMap(annos: Seq[TargetClkPortAnnoF]): ListMap[String, String] =
|
||||
ListMap(annos.map { x =>
|
||||
val target = x.target
|
||||
val absPath = {
|
||||
if (top == target.module.name) LowerName(target.name)
|
||||
else Seq(clkMods(target.module.name), LowerName(target.name)).mkString(".")
|
||||
}
|
||||
x.modId -> absPath
|
||||
}.sortBy(_._1): _*)
|
||||
|
||||
// ** clk port -> absolute path
|
||||
val clkSinks = convertClkPortAnnoToMap(clkSinksTemp)
|
||||
val clkSrcs = convertClkPortAnnoToMap(clkSrcsTemp)
|
||||
|
||||
clkSrcs foreach { case (id, path) =>
|
||||
require(allModClkPorts contains id, "All clock source properties must be defined by their respective modules") }
|
||||
|
||||
// Don't inline clock modules
|
||||
val modulesToInline = (c.modules.collect {
|
||||
case Module(_, n, _, _) if n != top && !clkModNames.contains(n) =>
|
||||
ModuleName(n, CircuitName(top))
|
||||
}).toSet
|
||||
|
||||
val inlineTransform = new InlineInstances
|
||||
val inlinedCircuit = inlineTransform.run(onlyClockCircuit, modulesToInline, Set(), None).circuit
|
||||
|
||||
val topModule = inlinedCircuit.modules.find(_.name == top).getOrElse(throwInternalError)
|
||||
|
||||
// Build a hashmap of connections to use for getOrigins
|
||||
val connects = getConnects(topModule)
|
||||
|
||||
// Clk sinks are either inputs to clock modules or top clk inputs --> separate
|
||||
// ** clk port -> absolute path
|
||||
val (topClks, clkModSinks) = clkSinks.partition {
|
||||
case (modId, absPath) if modId.split("\\.").head == top => true
|
||||
case _ => false
|
||||
}
|
||||
|
||||
// Must be 1:1 originally!
|
||||
def flipMapping(m: ListMap[String, String]): ListMap[String, String] =
|
||||
m.map { case (a, b) => b -> a }
|
||||
|
||||
val clkSrcsFlip = flipMapping(clkSrcs)
|
||||
val topClksFlip = flipMapping(topClks)
|
||||
|
||||
// Find origins of clk mod sinks
|
||||
val clkModSinkToSourceMap = clkModSinks.map { case (sinkId, sinkAbsPath) =>
|
||||
val sourceAbsPath = getOrigin(connects, sinkAbsPath).serialize
|
||||
val sourceId = {
|
||||
// sources of sinks are generated clks or top level clk inputs
|
||||
if (clkSrcsFlip.contains(sourceAbsPath)) clkSrcsFlip(sourceAbsPath)
|
||||
else if (topClksFlip.contains(sourceAbsPath)) topClksFlip(sourceAbsPath)
|
||||
else throw new Exception(s"Absolute path $sourceAbsPath of clk source for $sinkId not found!")
|
||||
}
|
||||
sinkId -> sourceId
|
||||
}
|
||||
|
||||
c.modules.foreach {
|
||||
case mod: DefModule =>
|
||||
mod.ports.foreach {
|
||||
case Port(_, n, dir, tpe)
|
||||
if tpe == ClockType &&
|
||||
((dir == Input && mod.name == top) || (dir == Output && clkModNames.contains(mod.name))) =>
|
||||
clkPortAnnos.find(x =>
|
||||
// TODO: Not sufficiently general for output clks? Might have forgotten to label a clk module...
|
||||
LowerName(x.target.name) == n && x.target.module.name == mod.name).getOrElse(
|
||||
throw new Exception(
|
||||
s"All top module input clks/clk module output clocks must be sinks/sources! $n not annotated!"))
|
||||
case _ =>
|
||||
}
|
||||
}
|
||||
|
||||
// Find sinks used to derive clk mod sources
|
||||
val clkModSourceToSinkMap: Seq[(String, Seq[String])] = clkModAnnos.map(x => {
|
||||
val modName = x.targetName
|
||||
x.generatedClks.map(y => Seq(modName, y.id).mkString(".") -> y.sources.map(z => Seq(modName, z).mkString(".")))
|
||||
} ).flatten
|
||||
|
||||
topClks.foreach {x => println(s"top clk: $x")}
|
||||
clkModSinks.foreach { x => println(s"clk sink: $x")}
|
||||
clkSrcs.foreach { x => println(s"gen clk: $x")}
|
||||
clkModSinkToSourceMap.foreach { x => println(s"sink -> src: $x")}
|
||||
clkModSourceToSinkMap.foreach { x => println(s"src -> dependent sinks: $x")}
|
||||
*/
|
||||
c
|
||||
}
|
||||
}
|
||||
@@ -1,9 +1,11 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package barstools.tapeout.transforms.pads
|
||||
|
||||
import chisel3._
|
||||
import barstools.tapeout.transforms.clkgen._
|
||||
import chisel3.experimental._
|
||||
import firrtl.transforms.DedupModules
|
||||
import firrtl.Transform
|
||||
import firrtl.annotations.Annotation
|
||||
|
||||
// TODO: Move out of pads
|
||||
|
||||
@@ -20,29 +22,12 @@ abstract class TopModule(
|
||||
coreHeight: Int = 0,
|
||||
usePads: Boolean = true,
|
||||
override_clock: Option[Clock] = None,
|
||||
override_reset: Option[Bool] = None) extends Module with IsClkModule {
|
||||
override_reset: Option[Bool] = None) extends Module {
|
||||
|
||||
override_clock.foreach(clock := _)
|
||||
override_reset.foreach(reset := _)
|
||||
|
||||
override def annotateClkPort(p: Element, anno: ClkPortAnnotation): Unit = {
|
||||
DataMirror.directionOf(p) match {
|
||||
case chisel3.core.ActualDirection.Input =>
|
||||
require(anno.tag.nonEmpty, "Top Module input clks must be clk sinks")
|
||||
require(anno.tag.get.src.nonEmpty,
|
||||
"Top module input clks must have clk period, etc. specified")
|
||||
case _ =>
|
||||
throw new Exception("Clk port direction must be specified!")
|
||||
}
|
||||
p match {
|
||||
case _: chisel3.core.Clock =>
|
||||
case _ => throw new Exception("Clock port must be of type Clock")
|
||||
}
|
||||
annotate(TargetClkPortAnnoC(p, anno))
|
||||
}
|
||||
|
||||
override def annotateDerivedClks(m: Module, anno: ClkModAnnotation): Unit =
|
||||
throw new Exception("Top module cannot be pure clock module!")
|
||||
private val mySelf = this
|
||||
|
||||
// Annotate module as top module (that requires pad transform)
|
||||
// Specify the yaml file that indicates how pads are templated,
|
||||
@@ -55,7 +40,38 @@ abstract class TopModule(
|
||||
coreHeight = coreHeight,
|
||||
supplyAnnos = supplyAnnos
|
||||
)
|
||||
annotate(TargetModulePadAnnoC(this, modulePadAnnotation))
|
||||
//TODO: PORT-1.4: Remove commented code
|
||||
// annotate(TargetModulePadAnnoC(this, modulePadAnnotation))
|
||||
annotate(new ChiselAnnotation with RunFirrtlTransform {
|
||||
override def toFirrtl: Annotation = {
|
||||
TargetModulePadAnnoF(mySelf.toNamed, modulePadAnnotation)
|
||||
}
|
||||
def transformClass: Class[_ <: Transform] = classOf[AddIOPadsTransform]
|
||||
})
|
||||
}
|
||||
|
||||
private def extractElementNames(signal: Data): Seq[String] = {
|
||||
val names = signal match {
|
||||
case elt: Record =>
|
||||
elt.elements.map { case (key, value) => extractElementNames(value).map(x => key + "_" + x) }.toSeq.flatten
|
||||
case elt: Vec[_] =>
|
||||
elt.zipWithIndex.map { case (elt, i) => extractElementNames(elt).map(x => i + "_" + x) }.toSeq.flatten
|
||||
case elt: Element => Seq("")
|
||||
case elt => throw new Exception(s"Cannot extractElementNames for type ${elt.getClass}")
|
||||
}
|
||||
names.map(s => s.stripSuffix("_"))
|
||||
}
|
||||
|
||||
// TODO: Replace!
|
||||
def extractElements(signal: Data): Seq[Element] = {
|
||||
signal match {
|
||||
case elt: Record =>
|
||||
elt.elements.map { case (key, value) => extractElements(value) }.toSeq.flatten
|
||||
case elt: Vec[_] =>
|
||||
elt.map { elt => extractElements(elt) }.toSeq.flatten
|
||||
case elt: Element => Seq(elt)
|
||||
case elt => throw new Exception(s"Cannot extractElements for type ${elt.getClass}")
|
||||
}
|
||||
}
|
||||
|
||||
// Annotate IO with side + pad name
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package barstools.tapeout.transforms.pads
|
||||
|
||||
import firrtl.annotations._
|
||||
import chisel3.experimental._
|
||||
import chisel3._
|
||||
import barstools.tapeout.transforms._
|
||||
import firrtl._
|
||||
|
||||
import net.jcazevedo.moultingyaml._
|
||||
|
||||
@@ -23,26 +23,32 @@ abstract class FirrtlPadTransformAnnotation {
|
||||
abstract class IOAnnotation {
|
||||
def serialize: String
|
||||
}
|
||||
|
||||
case class IOPadAnnotation(padSide: String, padName: String) extends IOAnnotation {
|
||||
import PadAnnotationsYaml._
|
||||
def serialize: String = this.toYaml.prettyPrint
|
||||
def getPadSide: PadSide = HasPadAnnotation.getSide(padSide)
|
||||
}
|
||||
|
||||
case class NoIOPadAnnotation(noPad: String = "") extends IOAnnotation {
|
||||
import PadAnnotationsYaml._
|
||||
def serialize: String = this.toYaml.prettyPrint
|
||||
def field = "noPad:"
|
||||
def field: String = "noPad:"
|
||||
}
|
||||
|
||||
// Firrtl version
|
||||
case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation) extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ComponentName] {
|
||||
case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation)
|
||||
extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ComponentName] {
|
||||
|
||||
def duplicate(n: ComponentName): TargetIOPadAnnoF = this.copy(target = n)
|
||||
def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize)
|
||||
def targetName = target.name
|
||||
def targetName: String = target.name
|
||||
}
|
||||
|
||||
//TODO: PORT-1.4: Remove commented code
|
||||
// Chisel version
|
||||
case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) extends ChiselAnnotation {
|
||||
def toFirrtl = TargetIOPadAnnoF(target.toNamed, anno)
|
||||
}
|
||||
//case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) extends ChiselAnnotation {
|
||||
// def toFirrtl = TargetIOPadAnnoF(target.toNamed, anno)
|
||||
//}
|
||||
|
||||
// A bunch of supply pads (designated by name, # on each chip side) can be associated with the top module
|
||||
case class SupplyAnnotation(
|
||||
@@ -51,6 +57,7 @@ case class SupplyAnnotation(
|
||||
rightSide: Int = 0,
|
||||
topSide: Int = 0,
|
||||
bottomSide: Int = 0)
|
||||
|
||||
// The chip top should have a default pad side, a pad template file, and supply annotations
|
||||
case class ModulePadAnnotation(
|
||||
defaultPadSide: String = Top.serialize,
|
||||
@@ -63,17 +70,16 @@ case class ModulePadAnnotation(
|
||||
require(supplyPadNames.distinct.length == supplyPadNames.length, "Supply pads should only be specified once!")
|
||||
def getDefaultPadSide: PadSide = HasPadAnnotation.getSide(defaultPadSide)
|
||||
}
|
||||
|
||||
// Firrtl version
|
||||
case class TargetModulePadAnnoF(target: ModuleName, anno: ModulePadAnnotation) extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ModuleName] {
|
||||
case class TargetModulePadAnnoF(target: ModuleName, anno: ModulePadAnnotation)
|
||||
extends FirrtlPadTransformAnnotation with SingleTargetAnnotation[ModuleName] {
|
||||
|
||||
def duplicate(n: ModuleName): TargetModulePadAnnoF = this.copy(target = n)
|
||||
def getAnno = Annotation(target, classOf[AddIOPadsTransform], anno.serialize)
|
||||
def targetName = target.name
|
||||
}
|
||||
// Chisel version
|
||||
case class TargetModulePadAnnoC(target: Module, anno: ModulePadAnnotation) extends ChiselAnnotation {
|
||||
def toFirrtl = TargetModulePadAnnoF(target.toNamed, anno)
|
||||
def targetName: String = target.name
|
||||
}
|
||||
|
||||
|
||||
case class CollectedAnnos(
|
||||
componentAnnos: Seq[TargetIOPadAnnoF],
|
||||
moduleAnnos: TargetModulePadAnnoF) {
|
||||
@@ -95,16 +101,34 @@ object HasPadAnnotation {
|
||||
case _ => throw new Exception(s" $a not a valid pad side annotation!")
|
||||
}
|
||||
|
||||
//TODO: PORT-1.4: Remove commented code
|
||||
// def unapply(a: Annotation): Option[FirrtlPadTransformAnnotation] = a match {
|
||||
// case Annotation(f, t, s) if t == classOf[AddIOPadsTransform] => f match {
|
||||
// case m: ModuleName =>
|
||||
// Some(TargetModulePadAnnoF(m, s.parseYaml.convertTo[ModulePadAnnotation]))
|
||||
// case c: ComponentName if s.contains(NoIOPadAnnotation().field) =>
|
||||
// Some(TargetIOPadAnnoF(c, s.parseYaml.convertTo[NoIOPadAnnotation]))
|
||||
// case c: ComponentName =>
|
||||
// Some(TargetIOPadAnnoF(c, s.parseYaml.convertTo[IOPadAnnotation]))
|
||||
// case _ => throw new Exception("Annotation only valid on module or component")
|
||||
// }
|
||||
// case _ => None
|
||||
// }
|
||||
|
||||
//scalastyle:off cyclomatic.complexity
|
||||
def unapply(a: Annotation): Option[FirrtlPadTransformAnnotation] = a match {
|
||||
case Annotation(f, t, s) if t == classOf[AddIOPadsTransform] => f match {
|
||||
case m: ModuleName =>
|
||||
Some(TargetModulePadAnnoF(m, s.parseYaml.convertTo[ModulePadAnnotation]))
|
||||
case c: ComponentName if s.contains(NoIOPadAnnotation().field) =>
|
||||
Some(TargetIOPadAnnoF(c, s.parseYaml.convertTo[NoIOPadAnnotation]))
|
||||
case c: ComponentName =>
|
||||
Some(TargetIOPadAnnoF(c, s.parseYaml.convertTo[IOPadAnnotation]))
|
||||
case _ => throw new Exception("Annotation only valid on module or component")
|
||||
}
|
||||
case hasTransform: RunFirrtlTransform if hasTransform.transformClass == classOf[AddIOPadsTransform] =>
|
||||
hasTransform match {
|
||||
case hasTarget: SingleTargetAnnotation[_] =>
|
||||
hasTarget.target match {
|
||||
case m: ModuleName =>
|
||||
Some(TargetModulePadAnnoF(m, s.parseYaml.convertTo[ModulePadAnnotation]))
|
||||
hasTarget match {
|
||||
case _ => None
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
case _ => None
|
||||
}
|
||||
|
||||
@@ -113,8 +137,9 @@ object HasPadAnnotation {
|
||||
val padAnnos = annos.map(x => unapply(x)).flatten
|
||||
val targets = padAnnos.map(x => x.targetName)
|
||||
require(targets.distinct.length == targets.length, "Only 1 pad related annotation is allowed per component/module")
|
||||
if (padAnnos.length == 0) None
|
||||
else {
|
||||
if (padAnnos.length == 0) {
|
||||
None
|
||||
} else {
|
||||
val moduleAnnosTemp = padAnnos.filter {
|
||||
case TargetModulePadAnnoF(_, _) => true
|
||||
case _ => false
|
||||
|
||||
@@ -1,181 +0,0 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package barstools.tapeout.transforms.clkgen
|
||||
|
||||
import chisel3._
|
||||
import firrtl._
|
||||
import org.scalatest.{FlatSpec, Matchers}
|
||||
import chisel3.experimental._
|
||||
import chisel3.iotesters._
|
||||
import chisel3.util.HasBlackBoxInline
|
||||
import barstools.tapeout.transforms.pads.TopModule
|
||||
|
||||
// Purely to see that clk src tagging works with BBs
|
||||
class FakeBBClk extends BlackBox with HasBlackBoxInline with IsClkModule {
|
||||
val io = IO(new Bundle {
|
||||
val inClk = Input(Clock())
|
||||
val outClk = Output(Vec(3, Clock()))
|
||||
})
|
||||
|
||||
annotateClkPort(io.inClk, Sink())
|
||||
val generatedClks = io.outClk.map { case elt =>
|
||||
val id = getIOName(elt)
|
||||
val srcId = getIOName(io.inClk)
|
||||
annotateClkPort(elt.asInstanceOf[Element])
|
||||
GeneratedClk(id, Seq(srcId), Seq(0, 1, 2))
|
||||
}.toSeq
|
||||
|
||||
annotateDerivedClks(ClkDiv, generatedClks)
|
||||
|
||||
// Generates a "FakeBB.v" file with the following Verilog module
|
||||
setInline("FakeBBClk.v",
|
||||
s"""
|
||||
|module FakeBBClk(
|
||||
| input inClk,
|
||||
| output outClk_0,
|
||||
| output outClk_1,
|
||||
| output outClk_2
|
||||
|);
|
||||
| always @* begin
|
||||
| outClk_0 = inClk;
|
||||
| outClk_1 = inClk;
|
||||
| outClk_2 = inClk;
|
||||
| end
|
||||
|endmodule
|
||||
""".stripMargin)
|
||||
}
|
||||
|
||||
class ModWithNestedClkIO(numPhases: Int) extends Bundle {
|
||||
val inClk = Input(Clock())
|
||||
val bbOutClk = Output(Vec(3, Clock()))
|
||||
val clkDivOut = Output(Vec(numPhases, Clock()))
|
||||
}
|
||||
|
||||
class TestModWithNestedClkIO(numPhases: Int) extends Bundle {
|
||||
val bbOutClk = Output(Vec(3, Bool()))
|
||||
val clkDivOut = Output(Vec(numPhases, Bool()))
|
||||
}
|
||||
|
||||
class ModWithNestedClk(divBy: Int, phases: Seq[Int], syncReset: Boolean) extends Module {
|
||||
|
||||
val io = IO(new ModWithNestedClkIO(phases.length))
|
||||
|
||||
val bb = Module(new FakeBBClk)
|
||||
bb.io.inClk := io.inClk
|
||||
io.bbOutClk := bb.io.outClk
|
||||
val clkDiv = Module(new SEClkDivider(divBy, phases, syncReset = syncReset))
|
||||
clkDiv.io.reset := reset
|
||||
clkDiv.io.inClk := io.inClk
|
||||
phases.zipWithIndex.foreach { case (phase, idx) => io.clkDivOut(idx) := clkDiv.io.outClks(phase) }
|
||||
|
||||
}
|
||||
|
||||
class TopModuleWithClks(val divBy: Int, val phases: Seq[Int]) extends TopModule(usePads = false) {
|
||||
val io = IO(new Bundle {
|
||||
val gen1 = new TestModWithNestedClkIO(phases.length)
|
||||
val gen2 = new TestModWithNestedClkIO(phases.length)
|
||||
val gen3 = new TestModWithNestedClkIO(phases.length)
|
||||
val fakeClk1 = Input(Clock())
|
||||
val fakeClk2 = Input(Clock())
|
||||
})
|
||||
|
||||
// TODO: Don't have to type Some
|
||||
annotateClkPort(clock,
|
||||
id = "clock", // not in io bundle
|
||||
sink = Sink(Some(ClkSrc(period = 5.0, async = Seq(getIOName(io.fakeClk1)))))
|
||||
)
|
||||
annotateClkPort(io.fakeClk1, Sink(Some(ClkSrc(period = 4.0))))
|
||||
annotateClkPort(io.fakeClk2, Sink(Some(ClkSrc(period = 3.0))))
|
||||
|
||||
// Most complicated: test chain of clock generators
|
||||
val gen1 = Module(new ModWithNestedClk(divBy, phases, syncReset = true))
|
||||
io.gen1.bbOutClk := Vec(gen1.io.bbOutClk.map(x => x.asUInt))
|
||||
io.gen1.clkDivOut := Vec(gen1.io.clkDivOut.map(x => x.asUInt))
|
||||
gen1.io.inClk := clock
|
||||
// ClkDiv on generated clk -> reset occurs before first input clk edge
|
||||
val gen2 = Module(new ModWithNestedClk(divBy, phases, syncReset = false))
|
||||
io.gen2.bbOutClk := Vec(gen2.io.bbOutClk.map(x => x.asUInt))
|
||||
io.gen2.clkDivOut := Vec(gen2.io.clkDivOut.map(x => x.asUInt))
|
||||
gen2.io.inClk := gen1.io.clkDivOut.last
|
||||
val gen3 = Module(new ModWithNestedClk(divBy, phases, syncReset = false))
|
||||
io.gen3.bbOutClk := Vec(gen3.io.bbOutClk.map(x => x.asUInt))
|
||||
io.gen3.clkDivOut := Vec(gen3.io.clkDivOut.map(x => x.asUInt))
|
||||
gen3.io.inClk := gen1.io.clkDivOut.last
|
||||
}
|
||||
|
||||
class TopModuleWithClksTester(c: TopModuleWithClks) extends PeekPokeTester(c) {
|
||||
val maxT = c.divBy * c.divBy * 4
|
||||
val numSubClkOutputs = c.io.gen1.clkDivOut.length
|
||||
val gen1Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
|
||||
val gen2Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
|
||||
val gen3Out = Seq.fill(numSubClkOutputs)(scala.collection.mutable.ArrayBuffer[Int]())
|
||||
reset(10)
|
||||
for (t <- 0 until maxT) {
|
||||
for (k <- 0 until numSubClkOutputs) {
|
||||
gen1Out(k) += peek(c.io.gen1.clkDivOut(k)).intValue
|
||||
gen2Out(k) += peek(c.io.gen2.clkDivOut(k)).intValue
|
||||
gen3Out(k) += peek(c.io.gen3.clkDivOut(k)).intValue
|
||||
}
|
||||
step(1)
|
||||
}
|
||||
|
||||
val clkCounts = (0 until maxT)
|
||||
val clkCountsModDiv = clkCounts.map(_ % c.divBy)
|
||||
for (k <- 0 until numSubClkOutputs) {
|
||||
val expected = clkCountsModDiv.map(x => if (x == c.phases(k)) 1 else 0)
|
||||
expect(gen1Out(k) == expected, s"gen1Out($k) incorrect!")
|
||||
println(s"gen1Out($k): \t${gen1Out(k).mkString("")}")
|
||||
}
|
||||
|
||||
val gen1ClkCounts = (0 until maxT/c.divBy).map(i => Seq.fill(c.divBy)(i)).flatten
|
||||
val gen1ClkCountsModDiv = gen1ClkCounts.map(_ % c.divBy)
|
||||
|
||||
for (k <- 0 until numSubClkOutputs) {
|
||||
// Handle initial transient
|
||||
val fillVal = if (c.phases.last == c.divBy - 1 && k == numSubClkOutputs - 1) 1 else 0
|
||||
val expected = Seq.fill(c.phases.last)(fillVal) ++
|
||||
gen1ClkCountsModDiv.map(x => if (x == c.phases(k)) 1 else 0).dropRight(c.phases.last)
|
||||
expect(gen2Out(k) == expected, s"gen1Out($k) incorrect!")
|
||||
println(s"gen2Out($k): \t${gen2Out(k).mkString("")}")
|
||||
println(s"expected: \t${expected.mkString("")}")
|
||||
}
|
||||
|
||||
expect(gen2Out == gen3Out, "gen2Out should equal gen3Out")
|
||||
|
||||
}
|
||||
|
||||
class ClkGenSpec extends FlatSpec with Matchers {
|
||||
|
||||
def readOutputFile(dir: String, f: String): String =
|
||||
scala.io.Source.fromFile(Seq(dir, f).mkString("/")).getLines.mkString("\n")
|
||||
def readResource(resource: String): String = {
|
||||
val stream = getClass.getResourceAsStream(resource)
|
||||
scala.io.Source.fromInputStream(stream).mkString
|
||||
}
|
||||
|
||||
def checkOutputs(dir: String) = {
|
||||
}
|
||||
|
||||
behavior of "top module with clk gens"
|
||||
|
||||
it should "pass simple testbench" in {
|
||||
val optionsManager = new TesterOptionsManager {
|
||||
firrtlOptions = firrtlOptions.copy(
|
||||
compilerName = "verilog"
|
||||
/*annotations = List(passes.clocklist.ClockListAnnotation(
|
||||
s"-c:TopModuleWithClks:-m:TopModuleWithClks:-o:test.clk"
|
||||
)),
|
||||
customTransforms = Seq(new passes.clocklist.ClockListTransform())*/
|
||||
)
|
||||
testerOptions = testerOptions.copy(isVerbose = false, backendName = "verilator", displayBase = 10)
|
||||
commonOptions = commonOptions.copy(targetDirName = "test_run_dir/ClkTB")
|
||||
}
|
||||
// WARNING: TB requires that phase divBy - 1 should be at the end of the Seq to be OK during initial transient
|
||||
iotesters.Driver.execute(() => new TopModuleWithClks(4, Seq(0, 1, 3)), optionsManager) { c =>
|
||||
val dir = optionsManager.commonOptions.targetDirName
|
||||
checkOutputs(dir)
|
||||
new TopModuleWithClksTester(c)
|
||||
} should be (true)
|
||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user