add test case

2019-10-28 13:45:05 -07:00
parent 7f0828cb30
commit be3b05a909
3 changed files with 143 additions and 31 deletions
--- a/macros/src/main/scala/MacroCompiler.scala
+++ b/macros/src/main/scala/MacroCompiler.scala
@@ -772,37 +772,38 @@ object MacroCompiler extends App {
  ) ++ modeOptions) mkString "\n"

  def parseArgs(map: MacroParamMap, costMap: CostParamMap, forcedMemories: ForcedMemories,
-                args: List[String]): (MacroParamMap, CostParamMap, ForcedMemories) =
-    args match {
-      case Nil => (map, costMap, forcedMemories)
-      case ("-n" | "--macro-conf") :: value :: tail =>
-        parseArgs(map + (Macros  -> value) + (MacrosFormat -> "conf"), costMap, forcedMemories, tail)
-      case ("-m" | "--macro-mdf") :: value :: tail =>
-        parseArgs(map + (Macros  -> value) + (MacrosFormat -> "mdf"), costMap, forcedMemories, tail)
-      case ("-l" | "--library") :: value :: tail =>
-        parseArgs(map + (Library -> value), costMap, forcedMemories, tail)
-      case ("-u" | "--use-compiler") :: tail =>
-        parseArgs(map + (UseCompiler -> ""), costMap, forcedMemories, tail)
-      case ("-v" | "--verilog") :: value :: tail =>
-        parseArgs(map + (Verilog -> value), costMap, forcedMemories, tail)
-      case ("-f" | "--firrtl") :: value :: tail =>
-        parseArgs(map + (Firrtl -> value), costMap, forcedMemories, tail)
-      case ("-hir" | "--hammer-ir") :: value :: tail =>
-        parseArgs(map + (HammerIR -> value), costMap, forcedMemories, tail)
-      case ("-c" | "--cost-func") :: value :: tail =>
-        parseArgs(map + (CostFunc -> value), costMap, forcedMemories, tail)
-      case ("-cp" | "--cost-param") :: value1 :: value2 :: tail =>
-        parseArgs(map, costMap + (value1 -> value2), forcedMemories, tail)
-      case "--force-compile" :: value :: tail =>
-        parseArgs(map, costMap, forcedMemories.copy(_1 = forcedMemories._1 + value), tail)
-      case "--force-synflops" :: value :: tail =>
-        parseArgs(map, costMap, forcedMemories.copy(_2 = forcedMemories._2 + value), tail)
-      case "--mode" :: value :: tail =>
-        parseArgs(map + (Mode -> value), costMap, forcedMemories, tail)
-      case arg :: tail =>
-        println(s"Unknown field $arg\n")
-        println(usage)
-        sys.exit(1)
+                args: List[String]): (MacroParamMap, CostParamMap, ForcedMemories) = {
+      args match {
+        case Nil => (map, costMap, forcedMemories)
+        case ("-n" | "--macro-conf") :: value :: tail =>
+          parseArgs(map + (Macros  -> value) + (MacrosFormat -> "conf"), costMap, forcedMemories, tail)
+        case ("-m" | "--macro-mdf") :: value :: tail =>
+          parseArgs(map + (Macros  -> value) + (MacrosFormat -> "mdf"), costMap, forcedMemories, tail)
+        case ("-l" | "--library") :: value :: tail =>
+          parseArgs(map + (Library -> value), costMap, forcedMemories, tail)
+        case ("-u" | "--use-compiler") :: tail =>
+          parseArgs(map + (UseCompiler -> ""), costMap, forcedMemories, tail)
+        case ("-v" | "--verilog") :: value :: tail =>
+          parseArgs(map + (Verilog -> value), costMap, forcedMemories, tail)
+        case ("-f" | "--firrtl") :: value :: tail =>
+          parseArgs(map + (Firrtl -> value), costMap, forcedMemories, tail)
+        case ("-hir" | "--hammer-ir") :: value :: tail =>
+          parseArgs(map + (HammerIR -> value), costMap, forcedMemories, tail)
+        case ("-c" | "--cost-func") :: value :: tail =>
+          parseArgs(map + (CostFunc -> value), costMap, forcedMemories, tail)
+        case ("-cp" | "--cost-param") :: value1 :: value2 :: tail =>
+          parseArgs(map, costMap + (value1 -> value2), forcedMemories, tail)
+        case "--force-compile" :: value :: tail =>
+          parseArgs(map, costMap, forcedMemories.copy(_1 = forcedMemories._1 + value), tail)
+        case "--force-synflops" :: value :: tail =>
+          parseArgs(map, costMap, forcedMemories.copy(_2 = forcedMemories._2 + value), tail)
+        case "--mode" :: value :: tail =>
+          parseArgs(map + (Mode -> value), costMap, forcedMemories, tail)
+        case arg :: tail =>
+          println(s"Unknown field $arg\n")
+          println(usage)
+          sys.exit(1)
+      }
    }

  def run(args: List[String]) {
--- a/macros/src/test/resources/lib-MaskPortTest.json
+++ b/macros/src/test/resources/lib-MaskPortTest.json
@@ -0,0 +1,27 @@
+[
+  {
+    "type" : "sram",
+    "name" : "fake_mem",
+    "width" : 64,
+    "depth" : "512",
+    "mux" : 4,
+    "family" : "1rw",
+    "ports" : [ {
+        "address port name" : "addr",
+        "address port polarity" : "active high",
+        "clock port name" : "clk",
+        "clock port polarity" : "positive edge",
+        "write enable port name" : "wen",
+        "write enable port polarity" : "active high",
+        "read enable port name" : "ren",
+        "read enable port polarity" : "active high",
+        "output port name" : "dataout",
+        "output port polarity" : "active high",
+        "input port name" : "datain",
+        "input port polarity" : "active high",
+        "mask port name" : "mport",
+        "mask port polarity" : "active low",
+        "mask granularity" : 1
+    } ]
+  }
+]
--- a/macros/src/test/scala/SpecificExamples.scala
+++ b/macros/src/test/scala/SpecificExamples.scala
@@ -22,6 +22,90 @@ class GenerateSomeVerilog extends MacroCompilerSpec with HasSRAMGenerator with H
  }
 }

+class MaskPortTest extends MacroCompilerSpec with HasSRAMGenerator {
+  val mem = s"mem-MaskPortTest.json" // mem. you want to create
+  val lib = s"lib-MaskPortTest.json" // lib. of mems to create it
+  val v = s"MaskPortTest.json"
+
+  override val libPrefix = "macros/src/test/resources"
+
+  val memSRAMs = mdf.macrolib.Utils.readMDFFromString(
+"""
+[ {
+  "type" : "sram",
+  "name" : "cc_dir_ext",
+  "width" : 128,
+  "depth" : "512",
+  "mux" : 1,
+  "ports" : [ {
+    "address port name" : "RW0_addr",
+    "address port polarity" : "active high",
+    "clock port name" : "RW0_clk",
+    "clock port polarity" : "positive edge",
+    "write enable port name" : "RW0_wmode",
+    "write enable port polarity" : "active high",
+    "chip enable port name" : "RW0_en",
+    "chip enable port polarity" : "active high",
+    "output port name" : "RW0_rdata",
+    "output port polarity" : "active high",
+    "input port name" : "RW0_wdata",
+    "input port polarity" : "active high",
+    "mask port name" : "RW0_wmask",
+    "mask port polarity" : "active high",
+    "mask granularity" : 16
+  } ],
+  "family" : "1rw"
+} ]
+""").getOrElse(List())
+
+  writeToMem(mem, memSRAMs)
+
+  val output =
+"""
+circuit cc_dir_ext :
+  module cc_dir_ext :
+    input RW0_addr : UInt<9>
+    input RW0_clk : Clock
+    input RW0_wdata : UInt<128>
+    output RW0_rdata : UInt<128>
+    input RW0_en : UInt<1>
+    input RW0_wmode : UInt<1>
+    input RW0_wmask : UInt<8>
+
+    inst mem_0_0 of fake_mem
+    inst mem_0_1 of fake_mem
+    mem_0_0.clk <= RW0_clk
+    mem_0_0.addr <= RW0_addr
+    node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0)
+    mem_0_0.datain <= bits(RW0_wdata, 63, 0)
+    mem_0_0.ren <= and(not(RW0_wmode), UInt<1>("h1"))
+    mem_0_0.mport <= not(cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), bits(RW0_wmask, 0, 0)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
+    mem_0_0.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1"))
+    mem_0_1.clk <= RW0_clk
+    mem_0_1.addr <= RW0_addr
+    node RW0_rdata_0_1 = bits(mem_0_1.dataout, 63, 0)
+    mem_0_1.datain <= bits(RW0_wdata, 127, 64)
+    mem_0_1.ren <= and(not(RW0_wmode), UInt<1>("h1"))
+    mem_0_1.mport <= not(cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), bits(RW0_wmask, 4, 4)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
+    mem_0_1.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1"))
+    node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
+    RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
+
+  extmodule fake_mem :
+    input addr : UInt<9>
+    input clk : Clock
+    input datain : UInt<64>
+    output dataout : UInt<64>
+    input ren : UInt<1>
+    input wen : UInt<1>
+    input mport : UInt<64>
+
+    defname = fake_mem
+"""
+
+  compileExecuteAndTest(mem, lib, v, output)
+}
+
 class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
  val mem = s"mem-BOOMTest.json"
  val lib = s"lib-BOOMTest.json"