Make the directory structure match the packages
All tests run as they did prior to the changes
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@@ -67,8 +67,9 @@ object OldMetric extends CostMetric with CostMetricCompanion {
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*/
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class ExternalMetric(path: String) extends CostMetric {
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import mdf.macrolib.Utils.writeMacroToPath
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import java.io._
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import scala.language.postfixOps // for !! postfix op
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import scala.language.postfixOps
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import sys.process._
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override def cost(mem: Macro, lib: Macro): Option[Double] = {
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@@ -8,18 +8,17 @@
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package barstools.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import barstools.macros.Utils._
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import firrtl.CompilerUtils.getLoweringTransforms
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import firrtl.Utils._
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import firrtl.annotations._
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import firrtl.transforms.{NoDCEAnnotation}
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import firrtl.CompilerUtils.getLoweringTransforms
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import mdf.macrolib.{PolarizedPort, PortPolarity, SRAMMacro, SRAMGroup, SRAMCompiler}
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import scala.collection.mutable.{ArrayBuffer, HashMap}
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import firrtl.ir._
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import firrtl.{PrimOps, _}
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import mdf.macrolib._
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import java.io.{File, FileWriter}
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import scala.io.{Source}
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import Utils._
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import scala.collection.mutable.{ArrayBuffer, HashMap}
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import scala.io.Source
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case class MacroCompilerException(msg: String) extends Exception(msg)
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@@ -2,11 +2,11 @@
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package barstools.macros
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import barstools.macros.Utils._
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import firrtl.Utils._
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import firrtl._
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import firrtl.ir._
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import firrtl.Utils._
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import firrtl.passes.MemPortUtils.{memPortField, memType}
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import Utils._
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import firrtl.passes.MemPortUtils.memPortField
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class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
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val extraMods = scala.collection.mutable.ArrayBuffer.empty[Module]
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@@ -2,14 +2,12 @@
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package barstools.macros
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import firrtl._
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import firrtl.ir._
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import firrtl.PrimOps
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import firrtl.passes.memlib.{MemConf, MemPort, ReadPort, WritePort, ReadWritePort, MaskedWritePort, MaskedReadWritePort}
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import firrtl.Utils.BoolType
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import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
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import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge, MacroExtraPort}
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import java.io.File
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import firrtl.ir._
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import firrtl.passes.memlib._
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import firrtl.{PrimOps, _}
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import mdf.macrolib.{Input => _, Output => _, _}
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import scala.language.implicitConversions
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object MacroCompilerMath {
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@@ -2,14 +2,13 @@
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package barstools.macros
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import firrtl.Parser.parse
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import firrtl.ir.{Circuit, NoInfo}
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import firrtl.passes.RemoveEmpty
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import firrtl.Parser.parse
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import java.io.{File, StringWriter}
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import mdf.macrolib.SRAMMacro
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import java.io.File
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abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
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import scala.language.implicitConversions
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implicit def String2SomeString(i: String): Option[String] = Some(i)
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@@ -122,6 +121,7 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
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// A collection of standard SRAM generators.
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trait HasSRAMGenerator {
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import mdf.macrolib._
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import scala.language.implicitConversions
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implicit def Int2SomeInt(i: Int): Option[Int] = Some(i)
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implicit def BigInt2SomeBigInt(i: BigInt): Option[BigInt] = Some(i)
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@@ -1,7 +1,5 @@
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package barstools.macros
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import mdf.macrolib._
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// Test the ability of the compiler to deal with various mask combinations.
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trait MasksTestSettings {
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@@ -1,7 +1,5 @@
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package barstools.macros
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import mdf.macrolib._
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class SRAMCompiler extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
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val compiler = generateSRAMCompiler("awesome", "A")
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val verilog = s"v-SRAMCompiler.v"
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@@ -1,7 +1,5 @@
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package barstools.macros
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import mdf.macrolib._
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// Test the depth splitting aspect of the memory compiler.
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// This file is for simple tests: one read-write port, powers of two sizes, etc.
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// For example, implementing a 4096x32 memory using four 1024x32 memories.
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