Make the directory structure match the packages

All tests run as they did prior to the changes
This commit is contained in:
chick
2021-02-03 17:46:12 -08:00
parent 0faa16d330
commit 19e51f3df5
31 changed files with 50 additions and 61 deletions

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@@ -67,8 +67,9 @@ object OldMetric extends CostMetric with CostMetricCompanion {
*/
class ExternalMetric(path: String) extends CostMetric {
import mdf.macrolib.Utils.writeMacroToPath
import java.io._
import scala.language.postfixOps // for !! postfix op
import scala.language.postfixOps
import sys.process._
override def cost(mem: Macro, lib: Macro): Option[Double] = {

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@@ -8,18 +8,17 @@
package barstools.macros
import firrtl._
import firrtl.ir._
import firrtl.PrimOps
import barstools.macros.Utils._
import firrtl.CompilerUtils.getLoweringTransforms
import firrtl.Utils._
import firrtl.annotations._
import firrtl.transforms.{NoDCEAnnotation}
import firrtl.CompilerUtils.getLoweringTransforms
import mdf.macrolib.{PolarizedPort, PortPolarity, SRAMMacro, SRAMGroup, SRAMCompiler}
import scala.collection.mutable.{ArrayBuffer, HashMap}
import firrtl.ir._
import firrtl.{PrimOps, _}
import mdf.macrolib._
import java.io.{File, FileWriter}
import scala.io.{Source}
import Utils._
import scala.collection.mutable.{ArrayBuffer, HashMap}
import scala.io.Source
case class MacroCompilerException(msg: String) extends Exception(msg)

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@@ -2,11 +2,11 @@
package barstools.macros
import barstools.macros.Utils._
import firrtl.Utils._
import firrtl._
import firrtl.ir._
import firrtl.Utils._
import firrtl.passes.MemPortUtils.{memPortField, memType}
import Utils._
import firrtl.passes.MemPortUtils.memPortField
class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
val extraMods = scala.collection.mutable.ArrayBuffer.empty[Module]

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@@ -2,14 +2,12 @@
package barstools.macros
import firrtl._
import firrtl.ir._
import firrtl.PrimOps
import firrtl.passes.memlib.{MemConf, MemPort, ReadPort, WritePort, ReadWritePort, MaskedWritePort, MaskedReadWritePort}
import firrtl.Utils.BoolType
import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge, MacroExtraPort}
import java.io.File
import firrtl.ir._
import firrtl.passes.memlib._
import firrtl.{PrimOps, _}
import mdf.macrolib.{Input => _, Output => _, _}
import scala.language.implicitConversions
object MacroCompilerMath {

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@@ -2,14 +2,13 @@
package barstools.macros
import firrtl.Parser.parse
import firrtl.ir.{Circuit, NoInfo}
import firrtl.passes.RemoveEmpty
import firrtl.Parser.parse
import java.io.{File, StringWriter}
import mdf.macrolib.SRAMMacro
import java.io.File
abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
import scala.language.implicitConversions
implicit def String2SomeString(i: String): Option[String] = Some(i)
@@ -122,6 +121,7 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
// A collection of standard SRAM generators.
trait HasSRAMGenerator {
import mdf.macrolib._
import scala.language.implicitConversions
implicit def Int2SomeInt(i: Int): Option[Int] = Some(i)
implicit def BigInt2SomeBigInt(i: BigInt): Option[BigInt] = Some(i)

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@@ -1,7 +1,5 @@
package barstools.macros
import mdf.macrolib._
// Test the ability of the compiler to deal with various mask combinations.
trait MasksTestSettings {

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@@ -1,7 +1,5 @@
package barstools.macros
import mdf.macrolib._
class SRAMCompiler extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
val compiler = generateSRAMCompiler("awesome", "A")
val verilog = s"v-SRAMCompiler.v"

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@@ -1,7 +1,5 @@
package barstools.macros
import mdf.macrolib._
// Test the depth splitting aspect of the memory compiler.
// This file is for simple tests: one read-write port, powers of two sizes, etc.
// For example, implementing a 4096x32 memory using four 1024x32 memories.