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Use the correct 'magic values' for the port names

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Ensure backwards compatiblity by using -m for MDF input and -n for conf
input. Also fix the naming scheme for memory ports.
This commit is contained in:
John Wright
2019-02-12 11:05:06 -08:00
committed by John Wright
parent d861fdd95c
commit f0c7bab3ea
2 changed files with 38 additions and 26 deletions
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28
macros/src/main/scala/MacroCompiler.scala
View File

@@ -74,13 +74,14 @@ object MacroCompilerAnnotation {
* Parameters associated to this MacroCompilerAnnotation.
*
* @param mem Path to memory lib
* @param memMode Type of memory lib (Some("conf"), Some("mdf"), or None (defaults to mdf))
* @param lib Path to library lib or None if no libraries
* @param costMetric Cost metric to use
* @param mode Compiler mode (see CompilerMode)
* @param forceCompile Set of memories to force compiling to lib regardless of the mode
* @param forceSynflops Set of memories to force compiling as flops regardless of the mode
*/
case class Params(mem: String, lib: Option[String], costMetric: CostMetric, mode: CompilerMode, useCompiler: Boolean,
case class Params(mem: String, memMode: Option[String], lib: Option[String], costMetric: CostMetric, mode: CompilerMode, useCompiler: Boolean,
forceCompile: Set[String], forceSynflops: Set[String])
/**
@@ -610,7 +611,7 @@ class MacroCompilerTransform extends Transform {
def execute(state: CircuitState) = getMyAnnotations(state) match {
case Seq(MacroCompilerAnnotation(state.circuit.main,
MacroCompilerAnnotation.Params(memFile, libFile, costMetric, mode, useCompiler, forceCompile, forceSynflops))) =>
MacroCompilerAnnotation.Params(memFile, memFileFormat, libFile, costMetric, mode, useCompiler, forceCompile, forceSynflops))) =>
if (mode == MacroCompilerAnnotation.FallbackSynflops) {
throw new UnsupportedOperationException("Not implemented yet")
}
@@ -619,7 +620,10 @@ class MacroCompilerTransform extends Transform {
assert((forceCompile intersect forceSynflops).isEmpty, "Cannot have modules both forced to compile and synflops")
// Read, eliminate None, get only SRAM, make firrtl macro
val mems: Option[Seq[Macro]] = Utils.readConfFromPath(Some(memFile)) match {
val mems: Option[Seq[Macro]] = (memFileFormat match {
case Some("conf") => Utils.readConfFromPath(Some(memFile))
case _ => mdf.macrolib.Utils.readMDFFromPath(Some(memFile))
}) match {
case Some(x:Seq[mdf.macrolib.Macro]) =>
Some(Utils.filterForSRAM(Some(x)) getOrElse(List()) map {new Macro(_)})
case _ => None
@@ -688,6 +692,7 @@ class MacroCompiler extends Compiler {
object MacroCompiler extends App {
sealed trait MacroParam
case object Macros extends MacroParam
case object MacrosFormat extends MacroParam
case object Library extends MacroParam
case object Verilog extends MacroParam
case object Firrtl extends MacroParam
@@ -702,7 +707,8 @@ object MacroCompiler extends App {
.map { case (_, cmd, description) => s" $cmd: $description" }
val usage: String = (Seq(
"Options:",
" -m, --macro-conf: The set of macros to compile in firrtl-generated conf format",
" -n, --macro-conf: The set of macros to compile in firrtl-generated conf format (exclusive with -m)",
" -m, --macro-mdf: The set of macros to compile in MDF JSON format (exclusive with -n)",
" -l, --library: The set of macros that have blackbox instances",
" -u, --use-compiler: Flag, whether to use the memory compiler defined in library",
" -v, --verilog: Verilog output",
@@ -718,8 +724,10 @@ object MacroCompiler extends App {
args: List[String]): (MacroParamMap, CostParamMap, ForcedMemories) =
args match {
case Nil => (map, costMap, forcedMemories)
case ("-m" | "--macro-conf") :: value :: tail =>
parseArgs(map + (Macros -> value), costMap, forcedMemories, tail)
case ("-n" | "--macro-conf") :: value :: tail =>
parseArgs(map + (Macros -> value) + (MacrosFormat -> "conf"), costMap, forcedMemories, tail)
case ("-m" | "--macro-mdf") :: value :: tail =>
parseArgs(map + (Macros -> value) + (MacrosFormat -> "mdf"), costMap, forcedMemories, tail)
case ("-l" | "--library") :: value :: tail =>
parseArgs(map + (Library -> value), costMap, forcedMemories, tail)
case ("-u" | "--use-compiler") :: tail =>
@@ -747,7 +755,11 @@ object MacroCompiler extends App {
def run(args: List[String]) {
val (params, costParams, forcedMemories) = parseArgs(Map[MacroParam, String](), Map[String, String](), (Set.empty, Set.empty), args)
try {
val macros = Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
val macros = if (params.get(MacrosFormat) == Some("conf")) {
Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
} else {
Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
}
if (macros.nonEmpty) {
// Note: the last macro in the input list is (seemingly arbitrarily)
@@ -757,7 +769,7 @@ object MacroCompiler extends App {
Seq(MacroCompilerAnnotation(
circuit.main,
MacroCompilerAnnotation.Params(
params.get(Macros).get, params.get(Library),
params.get(Macros).get, params.get(MacrosFormat), params.get(Library),
CostMetric.getCostMetric(params.getOrElse(CostFunc, "default"), costParams),
MacroCompilerAnnotation.stringToCompilerMode(params.getOrElse(Mode, "default")),
params.contains(UseCompiler),

36
macros/src/main/scala/Utils.scala
View File

@@ -92,9 +92,9 @@ object Utils {
numR += 1
MacroPort(
width=Some(width), depth=Some(depth),
address=PolarizedPort(s"${portName}_address", ActiveHigh),
clock=PolarizedPort(s"${portName}_clock", PositiveEdge),
readEnable=Some(PolarizedPort(s"${portName}_ren", ActiveHigh)),
address=PolarizedPort(s"${portName}_addr", ActiveHigh),
clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
output=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
) }
case WritePort => {
@@ -102,9 +102,9 @@ object Utils {
numW += 1
MacroPort(
width=Some(width), depth=Some(depth),
address=PolarizedPort(s"${portName}_address", ActiveHigh),
clock=PolarizedPort(s"${portName}_clock", PositiveEdge),
writeEnable=Some(PolarizedPort(s"${portName}_wen", ActiveHigh)),
address=PolarizedPort(s"${portName}_addr", ActiveHigh),
clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
) }
case MaskWritePort => {
@@ -112,9 +112,9 @@ object Utils {
numW += 1
MacroPort(
width=Some(width), depth=Some(depth),
address=PolarizedPort(s"${portName}_address", ActiveHigh),
clock=PolarizedPort(s"${portName}_clock", PositiveEdge),
writeEnable=Some(PolarizedPort(s"${portName}_wen", ActiveHigh)),
address=PolarizedPort(s"${portName}_addr", ActiveHigh),
clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
maskPort=Some(PolarizedPort(s"${portName}_mask", ActiveHigh)),
maskGran=maskGran,
input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
@@ -124,10 +124,10 @@ object Utils {
numRW += 1
MacroPort(
width=Some(width), depth=Some(depth),
address=PolarizedPort(s"${portName}_address", ActiveHigh),
clock=PolarizedPort(s"${portName}_clock", PositiveEdge),
writeEnable=Some(PolarizedPort(s"${portName}_wen", ActiveHigh)),
readEnable=Some(PolarizedPort(s"${portName}_ren", ActiveHigh)),
address=PolarizedPort(s"${portName}_addr", ActiveHigh),
clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
writeEnable=Some(PolarizedPort(s"${portName}_wmode", ActiveHigh)),
input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh))
) }
@@ -136,11 +136,11 @@ object Utils {
numRW += 1
MacroPort(
width=Some(width), depth=Some(depth),
address=PolarizedPort(s"${portName}_address", ActiveHigh),
clock=PolarizedPort(s"${portName}_clock", PositiveEdge),
writeEnable=Some(PolarizedPort(s"${portName}_wen", ActiveHigh)),
readEnable=Some(PolarizedPort(s"${portName}_ren", ActiveHigh)),
maskPort=Some(PolarizedPort(s"${portName}_mask", ActiveHigh)),
address=PolarizedPort(s"${portName}_addr", ActiveHigh),
clock=PolarizedPort(s"${portName}_clk", PositiveEdge),
chipEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
writeEnable=Some(PolarizedPort(s"${portName}_wmode", ActiveHigh)),
maskPort=Some(PolarizedPort(s"${portName}_wmask", ActiveHigh)),
maskGran=maskGran,
input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh))