Merge branch 'master' into bump_chisel_3.2.x

2020-02-19 18:05:16 -08:00
parent db0efd38fc 8ca876503c
commit a00771d33a
1 changed files with 2 additions and 1 deletions
--- a/macros/src/main/scala/MacroCompiler.scala
+++ b/macros/src/main/scala/MacroCompiler.scala
@@ -549,11 +549,12 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
      }
    }
    // Connect mem outputs
+    val zeroOutputValue: Expression = UIntLiteral(0, IntWidth(mem.src.width))
    mem.src.ports foreach { port =>
      port.output match {
        case Some(PolarizedPort(mem, _)) => outputs get mem match {
          case Some(select) =>
-            val output = (select foldRight (zero: Expression)) {
+            val output = (select foldRight (zeroOutputValue)) {
              case ((cond, tval), fval) => Mux(cond, tval, fval, fval.tpe) }
            stmts += Connect(NoInfo, WRef(mem), output)
          case None =>