 abejgonzalez
|
341a6cc48d
|
Merge remote-tracking branch 'origin/lazy-harnessbinders' into local-fpga-temp
|
2020-10-13 16:23:41 -07:00 |
|
|
abejgonzalez
|
5bbd865447
|
Add MMC Device section to the DTS
|
2020-10-13 16:18:00 -07:00 |
|
|
Jerry Zhao
|
9c298eedfe
|
Support evaluation of HarnessBinders in LazyModule context
|
2020-10-13 15:10:41 -07:00 |
|
|
Jerry Zhao
|
0c46ed1676
|
Rename testchip_fesvr to testchip_tsi
|
2020-10-09 09:34:20 -07:00 |
|
|
Jerry Zhao
|
25129c27ca
|
Add testchip_fesvr to uncondtionally used resources
|
2020-10-09 09:27:58 -07:00 |
|
|
Jerry Zhao
|
d71c3b6357
|
Unify htif implementation with firesim
|
2020-10-09 09:27:58 -07:00 |
|
|
David Biancolin
|
986b5831c8
|
[clocking] Sketch out a topology that puts the MBUS is a separate domain
|
2020-10-09 07:23:17 -07:00 |
|
|
David Biancolin
|
30b278687b
|
[clocking] Also aggregate clocks in AsyncClockGroup
|
2020-10-09 07:13:55 -07:00 |
|
|
dunn
|
252f9c6a12
|
Beginning to modify Arty TestHarness to conform with HarnessBinders. Currently does not compile; debugging.
|
2020-10-07 11:55:16 -07:00 |
|
|
David Biancolin
|
392d5b0801
|
[clocking] Synchronize all output clocks from DividerOnly generator
|
2020-10-07 09:32:48 -07:00 |
|
|
dunn
|
a67318928a
|
Bumping submodules to upstream dev's commits.
|
2020-10-07 09:02:30 -07:00 |
|
|
Zitao Fang
|
5282965b5b
|
Filter specified HTIF arguments and plusargs only
|
2020-10-06 15:50:11 -07:00 |
|
|
dunn
|
309b9ee7ae
|
Merge remote-tracking branch 'upstream/dev' into local-fpga-arty-abe
|
2020-10-06 12:23:18 -07:00 |
|
|
Zitao Fang
|
355e4ba606
|
Change to filter all arguments that begin with a '-'
|
2020-10-05 10:49:04 -07:00 |
|
|
Jerry Zhao
|
3d0022667a
|
Bump testchipip
|
2020-10-01 22:43:43 -07:00 |
|
|
Jerry Zhao
|
b057cfbd8c
|
Merge remote-tracking branch 'origin/dev' into clocking-features
|
2020-10-01 20:12:20 -07:00 |
|
|
Jerry ZhaoandGitHub
|
2db3c90f83
|
Merge pull request #648 from ucb-bar/sodor-integrate
Sodor Integration
|
2020-10-01 17:31:45 -07:00 |
|
|
Jerry Zhao
|
79042e4ce8
|
Bump to support firesim simulation of no-AXI4DRAM designs
|
2020-10-01 10:21:43 -07:00 |
|
|
Jerry Zhao
|
164617e2d6
|
Fix no-mbus example design
|
2020-10-01 10:20:10 -07:00 |
|
|
Jerry Zhao
|
489ae695fc
|
Add tile-resetter to all designs
|
2020-10-01 10:19:43 -07:00 |
|
|
Zitao Fang
|
6c33672c66
|
Bump Sodor submodule after merge
|
2020-10-01 10:08:39 -07:00 |
|
|
Albert Magyar
|
2f5790d611
|
Add model multi-threading annotations (ignored by default) to FireChip
|
2020-09-30 23:32:49 -07:00 |
|
|
Zitao Fang
|
ef03a5efe0
|
Bump testchipip
|
2020-09-30 14:36:45 -07:00 |
|
|
David Biancolin
|
ebfe3103a4
|
[clocks] IdealizedPll -> DividerOnlyClockGenerator
|
2020-09-29 17:33:49 -07:00 |
|
|
David Biancolin
|
5b414f5829
|
[clocks] Emit frequency summary for divider-only PLL model
|
2020-09-29 16:59:37 -07:00 |
|
|
David Biancolin
|
a6ce850391
|
[clocks] ClockDividerN: make first output edge occur on first input edge
|
2020-09-29 16:19:05 -07:00 |
|
|
Zitao Fang
|
2aac38b4c8
|
Fix CI bug
|
2020-09-27 23:15:10 -07:00 |
|
|
Zitao Fang
|
f7407709d2
|
Attempt to fix CI (2)
|
2020-09-25 21:31:12 -07:00 |
|
|
Zitao Fang
|
751c0c300e
|
Remove comments
|
2020-09-25 20:49:18 -07:00 |
|
|
Zitao Fang
|
5243ee2a35
|
Add HTIF args back to emulator.cc
|
2020-09-25 20:36:07 -07:00 |
|
|
David Biancolin
|
b76972d34b
|
Merge remote-tracking branch 'origin/dev' into diplomatic-clocks-pll-redux
|
2020-09-25 11:02:51 -07:00 |
|
|
David Biancolin
|
67145c6ccd
|
[clocking] Fix FireSim clock look up
|
2020-09-25 10:05:28 -07:00 |
|
|
David Biancolin
|
1b3514f95f
|
[clocks] Specify a default frequency for TraceGen
|
2020-09-25 10:03:46 -07:00 |
|
|
David Biancolin
|
7b8a954d04
|
[firechip] Rework FireSim clocking to be more similar to default CY targets
|
2020-09-24 23:32:07 -07:00 |
|
|
David Biancolin
|
cc949aadab
|
[clocking] Address some of Colin's PR comments
|
2020-09-24 23:28:47 -07:00 |
|
|
David Biancolin
|
f6989a1968
|
[clocks] Use the periphery frequency as the default
|
2020-09-24 23:24:08 -07:00 |
|
|
David Biancolin
|
96bf702c3b
|
[clocks] Factor out the PLL calculations into their own class
|
2020-09-24 23:23:11 -07:00 |
|
|
Zitao Fang
|
6641c1f983
|
Attempt to fix CI
|
2020-09-24 22:42:49 -07:00 |
|
|
David Biancolin
|
84195d28bb
|
[clocks] Don't override existing take frequency if present.
|
2020-09-23 15:29:52 -07:00 |
|
|
Zitao Fang
|
a02700a1d4
|
Add documentation for sodor
|
2020-09-18 23:14:47 -07:00 |
|
|
Zitao Fang
|
0c8771c35e
|
Merge branch 'dev' of github.com:ucb-bar/chipyard into sodor-integrate
|
2020-09-18 22:33:42 -07:00 |
|
|
Zitao Fang
|
a43400acb9
|
Update CI
|
2020-09-18 15:36:33 -07:00 |
|
|
David Biancolin
|
f36183d236
|
[clocks] Update AssignerKey name and comment
|
2020-09-18 11:28:31 -07:00 |
|
|
Jerry Zhao
|
b9622c5132
|
Merge remote-tracking branch 'origin/dev' into serial-tl
|
2020-09-18 01:00:13 -07:00 |
|
|
David Biancolin
|
ad147ec7f2
|
[clocks] Remove dealiaser and node injector until they are needed
|
2020-09-17 11:43:39 -07:00 |
|
|
David Biancolin
|
0f33ea3999
|
[clocks] Stringly specified clock frequencies; DRY out schemes
|
2020-09-17 11:41:05 -07:00 |
|
|
David Biancolin
|
6a26a350ee
|
[clocks] Update dealiaser based on feedback
|
2020-09-17 11:33:26 -07:00 |
|
|
David Biancolin
|
cfa7e30d95
|
[clocks] Fix comment in ClockDividerN
|
2020-09-17 11:32:51 -07:00 |
|
|
David Biancolin
|
b8d3e4a66d
|
Update Idealized PLL config
|
2020-09-16 16:30:25 -07:00 |
|
|
David Biancolin
|
8e4dedcecf
|
Remove require guard on divided configs
|
2020-09-16 16:30:00 -07:00 |
|