Commit Graph

179 Commits

Author SHA1 Message Date
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bb1ceffadd rebase master update 2021-07-30 21:03:14 -07:00
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b307c40ae7 mshr critical path optimization 2021-07-26 21:11:17 -07:00
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ea1e0f201e OUTPUT_REG refactoring 2021-07-23 06:58:37 -07:00
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1f94a1e673 minor update 2021-07-22 14:11:59 -07:00
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b3e54a837e minor update 2021-07-20 12:01:04 -07:00
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53b3d42908 cache's core response queue size control 2021-07-16 13:09:29 -07:00
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0bec734532 icache readonly optimization 2021-07-15 14:16:05 -07:00
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d9425cc484 cache elastic buffer optimization 2021-07-15 11:59:49 -07:00
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8678150ce0 cache multi-porting optimization 2021-07-15 11:54:27 -07:00
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10e9ee124b using onehot multiplexer to reduce critical path 2021-07-08 00:26:59 -07:00
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f84c8a0b5d instr_sched => ibuffer 2021-06-27 19:36:43 -07:00
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57143f5889 synthesis optimizations 2021-06-17 16:43:43 -07:00
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47c3234659 minor update 2021-06-13 10:58:48 -07:00
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5d2437d887 refactoring cache_config 2021-05-27 14:41:46 -07:00
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d8517d4d08 minor update 2021-05-26 13:37:07 -07:00
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04a1c0e9eb IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr 2021-05-01 13:44:08 -07:00
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8410c49f53 code refactoring: DRAM => MEM renaming 2021-04-26 00:58:48 -07:00
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aff5903a22 minor ibuffer critical path optimization. 2021-04-19 20:53:13 -07:00
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625689796f minor update 2021-04-04 23:42:57 -07:00
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062d02ddce Merge branch 'master' of https://github.gatech.edu/casl/Vortex 2021-03-04 20:51:03 -08:00
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3f5fd6d394 using shiftreg-based skid buffers 2021-02-28 02:20:09 -08:00
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700f9eea19 moving MUL unit into ALU unit 2021-02-23 13:49:02 -08:00
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7560202f8b cache bank refactoring - removing unecessary core response fifo & restoring single port data access 2021-02-21 21:47:46 -08:00
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ccb74ef286 cache data access with decoupled read/write ports 2021-02-21 15:18:24 -08:00
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05f93fac20 minor update 2021-02-20 13:15:15 -08:00
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9eed48435c instruction decode optimization 2021-02-14 00:19:54 -08:00
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3c37db877a cache specialization for in-order DRAM reponses 2021-02-13 20:23:29 -08:00
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665b97b810 multi-ported cache support for streaming 2021-02-08 16:13:32 -08:00
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111cc29482 minor update 2021-02-04 15:28:04 -08:00
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32b94f61f2 minor update 2021-02-01 11:00:09 -08:00
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62ff97d6e1 minor update - smem perf update 2021-02-01 10:29:20 -08:00
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dc18bfabb8 minor update - remove mshr data store 2021-01-30 06:40:48 -08:00
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5419859281 fcvt fix 2021-01-25 02:22:00 -08:00
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8775f63ec4 lkg build rollout with 16cores optimization on arria10 2021-01-24 16:49:22 -08:00
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74a687e395 minor updates 2021-01-18 05:43:30 -08:00
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a7f6b9fffc minor updates 2021-01-17 18:18:05 -08:00
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8b42393189 minor updates 2021-01-17 17:33:41 -08:00
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a046bd7a73 cache pipeline optimization 2021-01-17 17:19:52 -08:00
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ed216ab39d minor updates 2021-01-17 13:58:43 -08:00
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a69ba5ad7b cache flush support 2021-01-17 05:50:29 -08:00
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d4e7b28be8 cache refactoring 2021-01-17 00:18:56 -08:00
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4f26228d50 minor updates 2021-01-16 05:33:28 -08:00
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fcbf57b66a specialized shared memory module 2021-01-16 04:41:58 -08:00
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f146178c2d minor updates 2021-01-13 15:52:03 -08:00
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0e1650e1c2 bank deadlock fix 2021-01-13 15:51:42 -08:00
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79cc4d98e6 bank deadlock fix 2021-01-13 13:06:07 -08:00
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464c4f4bd8 minor updates 2021-01-12 20:16:59 -08:00
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e770824d47 fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance 2021-01-10 20:26:15 -08:00
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06945533cf fixed l2/l3 caches related bugs 2021-01-09 16:32:55 -08:00
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2058718f0f minor updates 2021-01-06 07:18:14 -08:00