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cache multi-porting optimization

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This commit is contained in:
Blaise Tine
2021-07-15 11:54:27 -07:00
parent c5aec572b5
commit 8678150ce0
4 changed files with 36 additions and 15 deletions
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7
hw/rtl/cache/VX_bank.v vendored
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@@ -50,7 +50,8 @@ module VX_bank #(
`endif
// Core Request
input wire [NUM_PORTS-1:0] core_req_valid,
input wire [NUM_PORTS-1:0] core_req_valid,
input wire [NUM_PORTS-1:0] core_req_pmask,
input wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] core_req_wsel,
input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] core_req_byteen,
input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_req_data,
@@ -108,7 +109,7 @@ module VX_bank #(
wire [`LINE_ADDR_WIDTH-1:0] creq_addr;
wire [CORE_TAG_WIDTH-1:0] creq_tag;
wire creq_push = (| core_req_valid) && core_req_ready;
wire creq_push = core_req_valid && core_req_ready;
assign core_req_ready = !creq_full;
VX_fifo_queue #(
@@ -120,7 +121,7 @@ module VX_bank #(
.reset (reset),
.push (creq_push),
.pop (creq_pop),
.data_in ({core_req_tag, core_req_rw, core_req_addr, core_req_valid, core_req_wsel, core_req_byteen, core_req_data, core_req_tid}),
.data_in ({core_req_tag, core_req_rw, core_req_addr, core_req_pmask, core_req_wsel, core_req_byteen, core_req_data, core_req_tid}),
.data_out ({creq_tag, creq_rw, creq_addr, creq_pmask, creq_wsel, creq_byteen, creq_data, creq_tid}),
.empty (creq_empty),
.full (creq_full),

9
hw/rtl/cache/VX_cache.v vendored
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@@ -290,6 +290,7 @@ module VX_cache #(
///////////////////////////////////////////////////////////////////////////
wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_valid;
wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask;
wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel;
wire [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data;
@@ -344,7 +345,8 @@ module VX_cache #(
.core_req_data (core_req_data_nc),
.core_req_tag (core_req_tag_nc),
.core_req_ready (core_req_ready_nc),
.per_bank_core_req_valid (per_bank_core_req_valid),
.per_bank_core_req_valid (per_bank_core_req_valid),
.per_bank_core_req_pmask (per_bank_core_req_pmask),
.per_bank_core_req_rw (per_bank_core_req_rw),
.per_bank_core_req_addr (per_bank_core_req_addr),
.per_bank_core_req_wsel (per_bank_core_req_wsel),
@@ -359,6 +361,7 @@ module VX_cache #(
for (genvar i = 0; i < NUM_BANKS; i++) begin
wire [NUM_PORTS-1:0] curr_bank_core_req_valid;
wire [NUM_PORTS-1:0] curr_bank_core_req_pmask;
wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] curr_bank_core_req_wsel;
wire [NUM_PORTS-1:0][WORD_SIZE-1:0] curr_bank_core_req_byteen;
wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] curr_bank_core_req_data;
@@ -389,6 +392,7 @@ module VX_cache #(
// Core Req
assign curr_bank_core_req_valid = per_bank_core_req_valid[i];
assign curr_bank_core_req_pmask = per_bank_core_req_pmask[i];
assign curr_bank_core_req_addr = per_bank_core_req_addr[i];
assign curr_bank_core_req_rw = per_bank_core_req_rw[i];
assign curr_bank_core_req_wsel = per_bank_core_req_wsel[i];
@@ -459,7 +463,8 @@ module VX_cache #(
`endif
// Core request
.core_req_valid (curr_bank_core_req_valid),
.core_req_valid (curr_bank_core_req_valid),
.core_req_pmask (curr_bank_core_req_pmask),
.core_req_rw (curr_bank_core_req_rw),
.core_req_byteen (curr_bank_core_req_byteen),
.core_req_addr (curr_bank_core_req_addr),

30
hw/rtl/cache/VX_core_req_bank_sel.v vendored
View File

@@ -35,7 +35,8 @@ module VX_core_req_bank_sel #(
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire [NUM_REQS-1:0] core_req_ready,
output wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_valid,
output wire [NUM_BANKS-1:0] per_bank_core_req_valid,
output wire [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask,
output wire [NUM_BANKS-1:0] per_bank_core_req_rw,
output wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr,
output wire [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel,
@@ -73,7 +74,8 @@ module VX_core_req_bank_sel #(
end
end
reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_valid_r;
reg [NUM_BANKS-1:0] per_bank_core_req_valid_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0] per_bank_core_req_pmask_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r;
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r;
@@ -86,6 +88,7 @@ module VX_core_req_bank_sel #(
if (NUM_REQS > 1) begin
if (NUM_PORTS > 1) begin
reg [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_line_addr_r;
wire [NUM_REQS-1:0] core_req_line_match;
@@ -107,7 +110,8 @@ module VX_core_req_bank_sel #(
reg [NUM_BANKS-1:0][NUM_PORTS-1:0][NUM_REQS-1:0] req_select_table_r;
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_valid_r = 0;
per_bank_core_req_pmask_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
@@ -119,7 +123,8 @@ module VX_core_req_bank_sel #(
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i];
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i];
per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i];
per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i];
per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i];
@@ -154,7 +159,8 @@ module VX_core_req_bank_sel #(
end else begin
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_valid_r = 0;
per_bank_core_req_pmask_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
@@ -164,8 +170,9 @@ module VX_core_req_bank_sel #(
per_bank_core_req_tid_r = 'x;
for (integer i = NUM_REQS-1; i >= 0; --i) begin
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i];
if (core_req_valid[i]) begin
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
per_bank_core_req_pmask_r[core_req_bid[i]][i % NUM_PORTS] = core_req_line_match[i];
per_bank_core_req_wsel_r[core_req_bid[i]][i % NUM_PORTS] = core_req_wsel[i];
per_bank_core_req_byteen_r[core_req_bid[i]][i % NUM_PORTS] = core_req_byteen[i];
per_bank_core_req_data_r[core_req_bid[i]][i % NUM_PORTS] = core_req_data[i];
@@ -203,7 +210,7 @@ module VX_core_req_bank_sel #(
end else begin
always @(*) begin
per_bank_core_req_valid_r = 0;
per_bank_core_req_valid_r = 0;
per_bank_core_req_rw_r = 'x;
per_bank_core_req_addr_r = 'x;
per_bank_core_req_wsel_r = 'x;
@@ -224,6 +231,8 @@ module VX_core_req_bank_sel #(
per_bank_core_req_tid_r[core_req_bid[i]] = `REQS_BITS'(i);
end
end
per_bank_core_req_pmask_r = per_bank_core_req_valid_r;
end
if (NUM_BANKS > 1) begin
@@ -275,6 +284,8 @@ module VX_core_req_bank_sel #(
per_bank_core_req_tag_r[core_req_bid[0]] = core_req_tag;
per_bank_core_req_tid_r[core_req_bid[0]] = 0;
core_req_ready_r = per_bank_core_req_ready[core_req_bid[0]];
per_bank_core_req_pmask_r = per_bank_core_req_valid_r;
end
end else begin
`UNUSED_VAR (core_req_bid)
@@ -288,12 +299,15 @@ module VX_core_req_bank_sel #(
per_bank_core_req_tag_r = core_req_tag;
per_bank_core_req_tid_r = 0;
core_req_ready_r = per_bank_core_req_ready;
per_bank_core_req_pmask_r = per_bank_core_req_valid_r;
end
end
end
assign per_bank_core_req_valid = per_bank_core_req_valid_r;
assign per_bank_core_req_pmask = per_bank_core_req_pmask_r;
assign per_bank_core_req_rw = per_bank_core_req_rw_r;
assign per_bank_core_req_addr = per_bank_core_req_addr_r;
assign per_bank_core_req_wsel = per_bank_core_req_wsel_r;

5
hw/rtl/cache/VX_shared_mem.v vendored
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@@ -91,11 +91,12 @@ module VX_shared_mem #(
.per_bank_core_req_tid (per_bank_core_req_tid_unqual),
.per_bank_core_req_rw (per_bank_core_req_rw_unqual),
.per_bank_core_req_addr (per_bank_core_req_addr_unqual),
`UNUSED_PIN (per_bank_core_req_wsel),
.per_bank_core_req_byteen(per_bank_core_req_byteen_unqual),
.per_bank_core_req_tag (per_bank_core_req_tag_unqual),
.per_bank_core_req_data (per_bank_core_req_data_unqual),
.per_bank_core_req_ready (per_bank_core_req_ready_unqual)
.per_bank_core_req_ready (per_bank_core_req_ready_unqual),
`UNUSED_PIN (per_bank_core_req_pmask),
`UNUSED_PIN (per_bank_core_req_wsel)
);
wire [NUM_BANKS-1:0] per_bank_core_req_valid;