599 lines
24 KiB
Verilog
599 lines
24 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_bank #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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// Number of Word requests per cycle
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parameter NUM_REQS = 1,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of bankS
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parameter NUM_BANKS = 1,
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// Number of ports per banks
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parameter NUM_PORTS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Core Request Queue Size
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parameter CREQ_SIZE = 1,
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// Miss Reserv Queue Knob
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parameter MSHR_SIZE = 1,
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// DRAM Response Queue Size
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parameter DRSQ_SIZE = 1,
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// DRAM Request Queue Size
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parameter DREQ_SIZE = 1,
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// Enable cache writeable
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parameter WRITE_ENABLE = 1,
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// core request tag size
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parameter CORE_TAG_WIDTH = 1,
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// size of tag id in core request tag
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parameter CORE_TAG_ID_BITS = 0,
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// bank offset from beginning of index range
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parameter BANK_ADDR_OFFSET = 0,
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// in-order DRAN
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parameter IN_ORDER_DRAM = 0
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) (
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`SCOPE_IO_VX_bank
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input wire clk,
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input wire reset,
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`ifdef PERF_ENABLE
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output wire perf_read_misses,
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output wire perf_write_misses,
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output wire perf_mshr_stalls,
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output wire perf_pipe_stalls,
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`endif
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// Core Request
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input wire [NUM_PORTS-1:0] core_req_valid,
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input wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] core_req_wsel,
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input wire [NUM_PORTS-1:0][WORD_SIZE-1:0] core_req_byteen,
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input wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_req_data,
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input wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_req_tid,
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input wire core_req_rw,
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input wire [`LINE_ADDR_WIDTH-1:0] core_req_addr,
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input wire [CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire core_req_ready,
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// Core Response
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output wire core_rsp_valid,
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output wire [NUM_PORTS-1:0] core_rsp_pmask,
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output wire [NUM_PORTS-1:0][`REQS_BITS-1:0] core_rsp_tid,
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output wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] core_rsp_data,
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output wire [CORE_TAG_WIDTH-1:0] core_rsp_tag,
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input wire core_rsp_ready,
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// DRAM request
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output wire dram_req_valid,
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output wire dram_req_rw,
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output wire [CACHE_LINE_SIZE-1:0] dram_req_byteen,
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output wire [`LINE_ADDR_WIDTH-1:0] dram_req_addr,
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output wire [`CACHE_LINE_WIDTH-1:0] dram_req_data,
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input wire dram_req_ready,
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// DRAM response
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input wire dram_rsp_valid,
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input wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr,
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input wire [`CACHE_LINE_WIDTH-1:0] dram_rsp_data,
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output wire dram_rsp_ready,
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// flush
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input wire flush_enable,
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input wire [`LINE_SELECT_BITS-1:0] flush_addr
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);
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`ifdef DBG_CACHE_REQ_INFO
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/* verilator lint_off UNUSED */
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wire [31:0] debug_pc_sel, debug_pc_st0, debug_pc_st1;
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wire [`NW_BITS-1:0] debug_wid_sel, debug_wid_st0, debug_wid_st1;
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/* verilator lint_on UNUSED */
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`endif
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wire creq_pop;
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wire creq_full;
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wire creq_empty;
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wire [NUM_PORTS-1:0] creq_pmask;
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wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] creq_wsel;
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] creq_byteen;
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wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] creq_data;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] creq_tid;
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wire creq_rw;
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wire [`LINE_ADDR_WIDTH-1:0] creq_addr;
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wire [CORE_TAG_WIDTH-1:0] creq_tag;
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wire creq_push = (| core_req_valid) && core_req_ready;
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assign core_req_ready = !creq_full;
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VX_fifo_queue #(
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.DATAW (CORE_TAG_WIDTH + 1 + `LINE_ADDR_WIDTH + (1 + `UP(`WORD_SELECT_BITS) + WORD_SIZE + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
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.SIZE (CREQ_SIZE),
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.BUFFERED (1)
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) core_req_queue (
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.clk (clk),
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.reset (reset),
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.push (creq_push),
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.pop (creq_pop),
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.data_in ({core_req_tag, core_req_rw, core_req_addr, core_req_valid, core_req_wsel, core_req_byteen, core_req_data, core_req_tid}),
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.data_out ({creq_tag, creq_rw, creq_addr, creq_pmask, creq_wsel, creq_byteen, creq_data, creq_tid}),
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.empty (creq_empty),
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.full (creq_full),
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`UNUSED_PIN (alm_empty),
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`UNUSED_PIN (alm_full),
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`UNUSED_PIN (size)
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);
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wire mshr_alm_full;
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wire mshr_push;
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wire mshr_pop;
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wire mshr_pending;
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wire mshr_valid;
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wire [`LINE_ADDR_WIDTH-1:0] mshr_addr;
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wire [CORE_TAG_WIDTH-1:0] mshr_tag;
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wire [NUM_PORTS-1:0] mshr_pmask;
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wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] mshr_wsel;
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] mshr_byteen;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] mshr_tid;
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wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1;
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wire mem_rw_st0, mem_rw_st1;
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wire [NUM_PORTS-1:0][`UP(`WORD_SELECT_BITS)-1:0] wsel_st0, wsel_st1;
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wire [NUM_PORTS-1:0][WORD_SIZE-1:0] byteen_st0, byteen_st1;
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wire [NUM_PORTS-1:0][`REQS_BITS-1:0] req_tid_st0, req_tid_st1;
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wire [NUM_PORTS-1:0] pmask_st0, pmask_st1;
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wire [`CACHE_LINE_WIDTH-1:0] rdata_st1;
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wire [`CACHE_LINE_WIDTH-1:0] wdata_st0, wdata_st1;
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wire [CORE_TAG_WIDTH-1:0] tag_st0, tag_st1;
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wire valid_st0, valid_st1;
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wire is_fill_st0, is_fill_st1;
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wire is_mshr_st0, is_mshr_st1;
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wire miss_st0, miss_st1;
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wire prev_miss_dep_st0;
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wire fill_req_unqual_st0, fill_req_unqual_st1;
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wire force_miss_st0, force_miss_st1;
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wire writeen_unqual_st0, writeen_unqual_st1;
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wire incoming_fill_st0, incoming_fill_st1;
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wire mshr_pending_st0;
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wire is_flush_st0;
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wire crsq_in_valid, crsq_in_ready, crsq_in_stall;
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wire dreq_alm_full;
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wire drsq_pop;
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wire crsq_in_fire = crsq_in_valid && crsq_in_ready;
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VX_pending_size #(
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.SIZE (MSHR_SIZE)
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) mshr_pending_size (
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.clk (clk),
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.reset (reset),
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.push (creq_pop && !creq_rw),
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.pop (crsq_in_fire),
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.full (mshr_alm_full),
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`UNUSED_PIN (empty),
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`UNUSED_PIN (size)
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);
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// determine which queue to pop next in priority order
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wire mshr_pop_unqual = mshr_valid
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&& !dreq_alm_full; // ensure DRAM request queue not full (deadlock prevention)
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wire drsq_pop_unqual = !mshr_pop_unqual && dram_rsp_valid;
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wire creq_pop_unqual = !mshr_pop_unqual && !drsq_pop_unqual && !creq_empty && !flush_enable;
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wire is_miss_st1 = valid_st1 && (miss_st1 || force_miss_st1);
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assign mshr_pop = mshr_pop_unqual
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&& !(!IN_ORDER_DRAM && is_miss_st1 && is_mshr_st1) // do not schedule another mshr request if the previous one missed
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&& !crsq_in_stall; // ensure core response ready
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assign drsq_pop = drsq_pop_unqual
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&& !crsq_in_stall; // ensure core response ready
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assign creq_pop = creq_pop_unqual
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&& !dreq_alm_full // ensure dram request ready
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&& !mshr_alm_full // ensure mshr enqueue ready
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&& !crsq_in_stall; // ensure core response ready
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assign dram_rsp_ready = drsq_pop;
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// we have a miss in mshr or entering it for the current address
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wire mshr_pending_sel = mshr_pending
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|| (is_miss_st1 && (creq_addr == addr_st1));
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`ifdef DBG_CACHE_REQ_INFO
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if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
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assign {debug_pc_sel, debug_wid_sel} = mshr_pop_unqual ? mshr_tag[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS] : creq_tag[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
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end else begin
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assign {debug_pc_sel, debug_wid_sel} = 0;
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end
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`endif
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wire [`CACHE_LINE_WIDTH-1:0] creq_line_data;
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if (`WORDS_PER_LINE > 1) begin
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if (NUM_PORTS > 1) begin
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reg [`CACHE_LINE_WIDTH-1:0] creq_line_data_r;
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always @(*) begin
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creq_line_data_r = 'x;
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if (creq_pmask[p]) begin
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creq_line_data_r[creq_wsel[p] * `WORD_WIDTH +: `WORD_WIDTH] = creq_data[p];
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end
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end
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end
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assign creq_line_data = creq_line_data_r;
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end else begin
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assign creq_line_data = {`WORDS_PER_LINE{creq_data}};
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end
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end else begin
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assign creq_line_data = creq_data;
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end
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wire [`LINE_ADDR_WIDTH-1:0] dram_rsp_addr_qual;
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if (IN_ORDER_DRAM) begin
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`UNUSED_VAR (dram_rsp_addr)
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assign dram_rsp_addr_qual = mshr_addr;
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end else begin
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assign dram_rsp_addr_qual = dram_rsp_addr;
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end
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH + 1 + 1),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (!crsq_in_stall),
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.data_in ({
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flush_enable || mshr_pop || drsq_pop || creq_pop,
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flush_enable,
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mshr_pop_unqual,
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drsq_pop_unqual || flush_enable,
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mshr_pop_unqual ? 1'b0 : creq_rw,
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mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr_qual : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
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dram_rsp_valid ? dram_rsp_data : creq_line_data,
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mshr_pop_unqual ? mshr_wsel : creq_wsel,
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mshr_pop_unqual ? mshr_byteen : creq_byteen,
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mshr_pop_unqual ? mshr_tid : creq_tid,
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mshr_pop_unqual ? mshr_pmask : creq_pmask,
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mshr_pop_unqual ? mshr_tag : creq_tag,
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mshr_pending_sel
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}),
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.data_out ({valid_st0, is_flush_st0, is_mshr_st0, is_fill_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0, mshr_pending_st0})
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);
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`ifdef DBG_CACHE_REQ_INFO
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if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
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assign {debug_pc_st0, debug_wid_st0} = tag_st0[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
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end else begin
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assign {debug_pc_st0, debug_wid_st0} = 0;
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end
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`endif
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wire tag_match_st0;
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VX_tag_access #(
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.BANK_ID (BANK_ID),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.BANK_ADDR_OFFSET (BANK_ADDR_OFFSET)
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) tag_access (
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.clk (clk),
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.reset (reset),
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`ifdef DBG_CACHE_REQ_INFO
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.debug_pc (debug_pc_st0),
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.debug_wid (debug_wid_st0),
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`endif
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// read/Fill
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.lookup (valid_st0 && !is_fill_st0),
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.addr (addr_st0),
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.fill (valid_st0 && is_fill_st0 && !crsq_in_stall),
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.is_flush (is_flush_st0),
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.tag_match (tag_match_st0)
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);
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// redundant fills
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wire is_redundant_fill_st0 = !IN_ORDER_DRAM && is_fill_st0 && tag_match_st0;
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// we had a miss with prior request for the current address
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assign prev_miss_dep_st0 = is_miss_st1 && (addr_st0 == addr_st1);
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assign miss_st0 = !is_fill_st0 && !tag_match_st0;
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// force miss to ensure commit order when a new request has pending previous requests to same block
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// also force a miss for mshr requests when previous requests got a miss
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assign force_miss_st0 = (!is_fill_st0 && !is_mshr_st0 && (mshr_pending_st0 || prev_miss_dep_st0))
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|| (is_mshr_st0 && is_mshr_st1 && is_miss_st1);
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assign writeen_unqual_st0 = (WRITE_ENABLE && !is_fill_st0 && tag_match_st0 && mem_rw_st0)
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|| (is_fill_st0 && !is_redundant_fill_st0);
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assign incoming_fill_st0 = dram_rsp_valid && (addr_st0 == dram_rsp_addr_qual);
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assign fill_req_unqual_st0 = !mem_rw_st0 && (!force_miss_st0 || (!IN_ORDER_DRAM && is_mshr_st0 && !prev_miss_dep_st0));
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VX_pipe_register #(
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.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH + (`UP(`WORD_SELECT_BITS) + WORD_SIZE + `REQS_BITS + 1) * NUM_PORTS + CORE_TAG_WIDTH),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (!crsq_in_stall),
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.data_in ({valid_st0, is_mshr_st0, is_fill_st0, writeen_unqual_st0, fill_req_unqual_st0, incoming_fill_st0, miss_st0, force_miss_st0, mem_rw_st0, addr_st0, wdata_st0, wsel_st0, byteen_st0, req_tid_st0, pmask_st0, tag_st0}),
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.data_out ({valid_st1, is_mshr_st1, is_fill_st1, writeen_unqual_st1, fill_req_unqual_st1, incoming_fill_st1, miss_st1, force_miss_st1, mem_rw_st1, addr_st1, wdata_st1, wsel_st1, byteen_st1, req_tid_st1, pmask_st1, tag_st1})
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);
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`ifdef DBG_CACHE_REQ_INFO
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if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
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assign {debug_pc_st1, debug_wid_st1} = tag_st1[CORE_TAG_WIDTH-1:CORE_TAG_ID_BITS];
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end else begin
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assign {debug_pc_st1, debug_wid_st1} = 0;
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end
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`endif
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wire writeen_st1 = writeen_unqual_st1 && (is_fill_st1 || !force_miss_st1);
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wire crsq_push_st1 = !is_fill_st1 && !mem_rw_st1 && !miss_st1 && !force_miss_st1;
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wire mshr_push_st1 = !is_fill_st1 && !mem_rw_st1 && (miss_st1 || force_miss_st1);
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wire incoming_fill_qual_st1 = (dram_rsp_valid && (addr_st1 == dram_rsp_addr_qual))
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|| incoming_fill_st1;
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wire do_writeback_st1 = !is_fill_st1 && mem_rw_st1;
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wire dreq_push_st1 = (miss_st1 && fill_req_unqual_st1 && !incoming_fill_qual_st1)
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|| do_writeback_st1;
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wire [`WORDS_PER_LINE-1:0][WORD_SIZE-1:0] line_byteen_st1;
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if (`WORDS_PER_LINE > 1) begin
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reg [CACHE_LINE_SIZE-1:0] line_byteen_r;
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always @(*) begin
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line_byteen_r = 0;
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for (integer p = 0; p < NUM_PORTS; p++) begin
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if ((NUM_PORTS == 1) || pmask_st1[p]) begin
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line_byteen_r[wsel_st1[p] * WORD_SIZE +: WORD_SIZE] = byteen_st1[p];
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end
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end
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end
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assign line_byteen_st1 = line_byteen_r;
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end else begin
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assign line_byteen_st1 = byteen_st1;
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end
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VX_data_access #(
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.BANK_ID (BANK_ID),
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.CACHE_ID (CACHE_ID),
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.CACHE_SIZE (CACHE_SIZE),
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.CACHE_LINE_SIZE(CACHE_LINE_SIZE),
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.NUM_BANKS (NUM_BANKS),
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.WORD_SIZE (WORD_SIZE),
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.WRITE_ENABLE (WRITE_ENABLE)
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) data_access (
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.clk (clk),
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.reset (reset),
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`ifdef DBG_CACHE_REQ_INFO
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.debug_pc (debug_pc_st1),
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.debug_wid (debug_wid_st1),
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`endif
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.addr (addr_st1),
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// reading
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.readen (valid_st1 && !is_fill_st1 && !mem_rw_st1),
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.rdata (rdata_st1),
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// writing
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.writeen (valid_st1 && writeen_st1),
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.is_fill (is_fill_st1),
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.byteen (line_byteen_st1),
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.wdata (wdata_st1)
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);
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assign mshr_push = valid_st1 && mshr_push_st1;
|
|
wire mshr_dequeue = valid_st1 && is_mshr_st1 && !mshr_push_st1 && crsq_in_ready;
|
|
wire mshr_restore = !IN_ORDER_DRAM && is_mshr_st1;
|
|
`RUNTIME_ASSERT(!IN_ORDER_DRAM || !(mshr_push && mshr_restore), ("Oops!"))
|
|
|
|
// push a missed request as 'ready' if it was a forced miss that actually had a hit
|
|
// or the fill request for this block is comming
|
|
wire mshr_init_ready_state = !miss_st1 || incoming_fill_qual_st1;
|
|
|
|
// use dram rsp or core req address to lookup the mshr
|
|
wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = dram_rsp_valid ? dram_rsp_addr_qual : creq_addr;
|
|
|
|
VX_miss_resrv #(
|
|
.BANK_ID (BANK_ID),
|
|
.CACHE_ID (CACHE_ID),
|
|
.CORE_TAG_ID_BITS (CORE_TAG_ID_BITS),
|
|
.CACHE_LINE_SIZE (CACHE_LINE_SIZE),
|
|
.NUM_BANKS (NUM_BANKS),
|
|
.NUM_PORTS (NUM_PORTS),
|
|
.WORD_SIZE (WORD_SIZE),
|
|
.NUM_REQS (NUM_REQS),
|
|
.MSHR_SIZE (MSHR_SIZE),
|
|
.ALM_FULL (MSHR_SIZE-2),
|
|
.CORE_TAG_WIDTH (CORE_TAG_WIDTH)
|
|
) miss_resrv (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
|
|
`ifdef DBG_CACHE_REQ_INFO
|
|
.deq_debug_pc (debug_pc_sel),
|
|
.deq_debug_wid (debug_wid_sel),
|
|
.enq_debug_pc (debug_pc_st1),
|
|
.enq_debug_wid (debug_wid_st1),
|
|
`endif
|
|
|
|
// enqueue
|
|
.enqueue (mshr_push),
|
|
.enqueue_addr (addr_st1),
|
|
.enqueue_data ({wsel_st1, byteen_st1, tag_st1, req_tid_st1, pmask_st1}),
|
|
.enqueue_is_mshr (mshr_restore),
|
|
.enqueue_as_ready (mshr_init_ready_state),
|
|
`UNUSED_PIN (enqueue_almfull),
|
|
`UNUSED_PIN (enqueue_full),
|
|
|
|
// lookup
|
|
.lookup_ready (drsq_pop),
|
|
.lookup_addr (lookup_addr),
|
|
.lookup_match (mshr_pending),
|
|
|
|
// schedule
|
|
.schedule (mshr_pop),
|
|
.schedule_valid (mshr_valid),
|
|
.schedule_addr (mshr_addr),
|
|
.schedule_data ({mshr_wsel, mshr_byteen, mshr_tag, mshr_tid, mshr_pmask}),
|
|
|
|
// dequeue
|
|
.dequeue (mshr_dequeue)
|
|
);
|
|
|
|
// Enqueue core response
|
|
|
|
wire [NUM_PORTS-1:0] crsq_pmask;
|
|
wire [NUM_PORTS-1:0][`WORD_WIDTH-1:0] crsq_data;
|
|
wire [NUM_PORTS-1:0][`REQS_BITS-1:0] crsq_tid;
|
|
wire [CORE_TAG_WIDTH-1:0] crsq_tag;
|
|
|
|
assign crsq_in_valid = valid_st1 && crsq_push_st1;
|
|
assign crsq_in_stall = crsq_in_valid && !crsq_in_ready;
|
|
|
|
assign crsq_pmask = pmask_st1;
|
|
assign crsq_tid = req_tid_st1;
|
|
assign crsq_tag = tag_st1;
|
|
|
|
if (`WORDS_PER_LINE > 1) begin
|
|
for (genvar p = 0; p < NUM_PORTS; ++p) begin
|
|
assign crsq_data[p] = rdata_st1[wsel_st1[p] * `WORD_WIDTH +: `WORD_WIDTH];
|
|
end
|
|
end else begin
|
|
assign crsq_data = rdata_st1;
|
|
end
|
|
|
|
VX_skid_buffer #(
|
|
.DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
|
|
.BUFFERED (1)
|
|
) core_rsp_req (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.valid_in (crsq_in_valid),
|
|
.data_in ({crsq_tag, crsq_pmask, crsq_data, crsq_tid}),
|
|
.ready_in (crsq_in_ready),
|
|
.valid_out (core_rsp_valid),
|
|
.data_out ({core_rsp_tag, core_rsp_pmask, core_rsp_data, core_rsp_tid}),
|
|
.ready_out (core_rsp_ready)
|
|
);
|
|
|
|
// Enqueue DRAM request
|
|
|
|
wire [CACHE_LINE_SIZE-1:0] dreq_byteen;
|
|
wire [`LINE_ADDR_WIDTH-1:0] dreq_addr;
|
|
wire [`CACHE_LINE_WIDTH-1:0] dreq_data;
|
|
wire dreq_push, dreq_pop, dreq_empty, dreq_rw;
|
|
|
|
assign dreq_push = valid_st1 && dreq_push_st1;
|
|
|
|
assign dreq_pop = dram_req_valid && dram_req_ready;
|
|
|
|
assign dreq_rw = WRITE_ENABLE && do_writeback_st1;
|
|
assign dreq_byteen = dreq_rw ? line_byteen_st1 : {CACHE_LINE_SIZE{1'b1}};
|
|
assign dreq_addr = addr_st1;
|
|
assign dreq_data = wdata_st1;
|
|
|
|
VX_fifo_queue #(
|
|
.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
|
|
.SIZE (DREQ_SIZE),
|
|
.ALM_FULL (DREQ_SIZE-2)
|
|
) dram_req_queue (
|
|
.clk (clk),
|
|
.reset (reset),
|
|
.push (dreq_push),
|
|
.pop (dreq_pop),
|
|
.data_in ({dreq_rw, dreq_byteen, dreq_addr, dreq_data}),
|
|
.data_out ({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
|
|
.empty (dreq_empty),
|
|
.alm_full (dreq_alm_full),
|
|
`UNUSED_PIN (full),
|
|
`UNUSED_PIN (alm_empty),
|
|
`UNUSED_PIN (size)
|
|
);
|
|
|
|
assign dram_req_valid = !dreq_empty;
|
|
|
|
`SCOPE_ASSIGN (valid_st0, valid_st0);
|
|
`SCOPE_ASSIGN (valid_st1, valid_st1);
|
|
`SCOPE_ASSIGN (is_fill_st0, is_fill_st0);
|
|
`SCOPE_ASSIGN (is_mshr_st0, is_mshr_st0);
|
|
`SCOPE_ASSIGN (miss_st0, miss_st0);
|
|
`SCOPE_ASSIGN (force_miss_st0, force_miss_st0);
|
|
`SCOPE_ASSIGN (mshr_push, mshr_push);
|
|
`SCOPE_ASSIGN (crsq_in_stall, crsq_in_stall);
|
|
`SCOPE_ASSIGN (dreq_alm_full, dreq_alm_full);
|
|
`SCOPE_ASSIGN (mshr_alm_full, mshr_alm_full);
|
|
`SCOPE_ASSIGN (addr_st0, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID));
|
|
`SCOPE_ASSIGN (addr_st1, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
|
|
|
|
`ifdef PERF_ENABLE
|
|
assign perf_read_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && !mem_rw_st1;
|
|
assign perf_write_misses = valid_st1 && !is_fill_st1 && !is_mshr_st1 && miss_st1 && mem_rw_st1;
|
|
assign perf_pipe_stalls = crsq_in_stall || dreq_alm_full || mshr_alm_full;
|
|
assign perf_mshr_stalls = mshr_alm_full;
|
|
`endif
|
|
|
|
`ifdef DBG_PRINT_CACHE_BANK
|
|
always @(posedge clk) begin
|
|
/*if (valid_st1 && pmask_st1 == {NUM_PORTS{1'b1}}) begin
|
|
$display("%t: cache%0d:%0d full bank multi-porting - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
|
|
end*/
|
|
if (valid_st1 && !is_fill_st1 && miss_st1 && incoming_fill_qual_st1) begin
|
|
$display("%t: cache%0d:%0d miss with incoming fill - addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID));
|
|
assert(!is_mshr_st1);
|
|
end
|
|
if (crsq_in_stall || dreq_alm_full || mshr_alm_full) begin
|
|
$display("%t: cache%0d:%0d pipeline-stall: cwbq=%b, dwbq=%b, mshr=%b", $time, CACHE_ID, BANK_ID, crsq_in_stall, dreq_alm_full, mshr_alm_full);
|
|
end
|
|
if (flush_enable) begin
|
|
$display("%t: cache%0d:%0d flush: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(flush_addr, BANK_ID));
|
|
end
|
|
if (drsq_pop) begin
|
|
$display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_rsp_addr_qual, BANK_ID), dram_rsp_data);
|
|
end
|
|
if (mshr_pop) begin
|
|
$display("%t: cache%0d:%0d mshr-rd-req: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(mshr_addr, BANK_ID), mshr_tag, mshr_pmask, mshr_tid, mshr_byteen, debug_wid_sel, debug_pc_sel);
|
|
end
|
|
if (creq_pop) begin
|
|
if (creq_rw)
|
|
$display("%t: cache%0d:%0d core-wr-req: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, creq_data, debug_wid_sel, debug_pc_sel);
|
|
else
|
|
$display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(creq_addr, BANK_ID), creq_tag, creq_pmask, creq_tid, creq_byteen, debug_wid_sel, debug_pc_sel);
|
|
end
|
|
if (crsq_in_fire) begin
|
|
$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, pmask=%0b, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_pmask, crsq_tid, crsq_data, debug_wid_st1, debug_pc_st1);
|
|
end
|
|
if (dreq_push) begin
|
|
if (do_writeback_st1)
|
|
$display("%t: cache%0d:%0d writeback: addr=%0h, data=%0h, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), dreq_data, dreq_byteen, debug_wid_st1, debug_pc_st1);
|
|
else
|
|
$display("%t: cache%0d:%0d fill-req: addr=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dreq_addr, BANK_ID), debug_wid_st1, debug_pc_st1);
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule |