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icache readonly optimization

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This commit is contained in:
Blaise Tine
2021-07-15 14:16:05 -07:00
parent a8f9a2559d
commit 0bec734532
2 changed files with 5 additions and 3 deletions
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2
hw/rtl/cache/VX_bank.v vendored
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@@ -247,7 +247,7 @@ module VX_bank #(
mrsq_enable || flush_enable,
mshr_enable ? 1'b0 : creq_rw,
mshr_enable ? mshr_addr : (mem_rsp_valid ? mem_rsp_addr : (flush_enable ? `LINE_ADDR_WIDTH'(flush_addr) : creq_addr)),
mem_rsp_valid ? mem_rsp_data : creq_line_data,
(mem_rsp_valid || !WRITE_ENABLE) ? mem_rsp_data : creq_line_data,
mshr_enable ? mshr_wsel : creq_wsel,
mshr_enable ? mshr_byteen : creq_byteen,
mshr_enable ? mshr_tid : creq_tid,

6
hw/rtl/cache/VX_data_access.v vendored
View File

@@ -45,16 +45,18 @@ module VX_data_access #(
`UNUSED_VAR (reset)
`UNUSED_VAR (readen)
localparam BYTEENW = WRITE_ENABLE ? CACHE_LINE_SIZE : 1;
wire [`LINE_SELECT_BITS-1:0] line_addr;
wire [CACHE_LINE_SIZE-1:0] byte_enable;
assign line_addr = addr[`LINE_SELECT_BITS-1:0];
assign byte_enable = (WRITE_ENABLE && !is_fill) ? byteen : {CACHE_LINE_SIZE{1'b1}};
assign byte_enable = is_fill ? {CACHE_LINE_SIZE{1'b1}} : byteen;
VX_sp_ram #(
.DATAW (CACHE_LINE_SIZE * 8),
.SIZE (`LINES_PER_BANK),
.BYTEENW (CACHE_LINE_SIZE),
.BYTEENW (BYTEENW),
.RWCHECK (1)
) data_store (
.clk(clk),