minor update

2021-04-04 23:42:57 -07:00
parent 0ea22a059c
commit 625689796f
1 changed files with 2 additions and 1 deletions
--- a/hw/rtl/cache/VX_bank.v
+++ b/hw/rtl/cache/VX_bank.v
@@ -487,7 +487,8 @@ module VX_bank #(
    end

    VX_skid_buffer #(
-        .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS)
+        .DATAW (CORE_TAG_WIDTH + (1 + `WORD_WIDTH + `REQS_BITS) * NUM_PORTS),
+        .BUFFERED (NUM_BANKS == 1)
    ) core_rsp_req (
        .clk       (clk),
        .reset     (reset),