fix opae build

hw/Makefile

@@ -25,7 +25,7 @@ THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu
 .PHONY: build_config
 
 build_config:
-	./scripts/gen_config.py --outv ./rtl/VX_user_config.v --outc ./simulate/VX_config.h
+	./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h
 
 gen-singlecore: build_config
 	verilator $(VF) -DNDEBUG -cc $(SINGLE_CORE) -CFLAGS '$(CF) -DNDEBUG'

hw/modelsim/Makefile

@@ -6,9 +6,9 @@ ALL:sim
 SRC = \
   vortex_dpi.cpp  \
   vortex_tb.v \
-../rtl/VX_user_config.v \
+../rtl/VX_user_config.vh \
-../rtl/VX_config.v \
+../rtl/VX_config.vh \
-../rtl/VX_define.v \
+../rtl/VX_define.vh \
 ../rtl/interfaces/VX_branch_response_inter.v \
 ../rtl/interfaces/VX_csr_req_inter.v \
 ../rtl/interfaces/VX_csr_wb_inter.v \

hw/modelsim/vortex_tb.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 //`define NUM_BANKS 8
 //`define NUM_WORDS_PER_BLOCK 4

hw/opae/sources.txt

@@ -9,9 +9,9 @@ vortex_afu.json
 +incdir+../rtl/cache
 +incdir+../rtl/libs
 
-../rtl/VX_user_config.v
+../rtl/VX_user_config.vh
-../rtl/VX_config.v
+../rtl/VX_config.vh
-../rtl/VX_define.v
+../rtl/VX_define.vh
 ../rtl/cache/VX_cache_config.vh
 
 ../rtl/interfaces/VX_exec_unit_req_if.v

hw/rtl/.gitignore

@@ -1 +1 @@
-/VX_user_config.v
+/VX_user_config.vh

hw/rtl/VX_alu.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_alu (
 	input wire        clk,

hw/rtl/VX_back_end.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_back_end	#(
 	parameter CORE_ID = 0

hw/rtl/VX_config.vh

@@ -1,7 +1,7 @@
 `ifndef VX_CONFIG
 `define VX_CONFIG
 
-`include "VX_user_config.v"
+`include "VX_user_config.vh"
 
 `ifndef NUM_CLUSTERS
 `define NUM_CLUSTERS 1

hw/rtl/VX_csr_data.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 module VX_csr_data (
 	input wire clk,    // Clock

hw/rtl/VX_csr_pipe.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_csr_pipe #(
 	parameter CORE_ID = 0

hw/rtl/VX_csr_wrapper.v

@@ -1,5 +1,5 @@
 
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_csr_wrapper (
 	VX_csr_req_if csr_req_if,

hw/rtl/VX_decode.v

@@ -1,5 +1,5 @@
 
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_decode(
 	// Fetch Inputs

hw/rtl/VX_define.vh

@@ -1,7 +1,7 @@
 `ifndef VX_DEFINE
 `define VX_DEFINE
 
-`include "./VX_config.v"
+`include "./VX_config.vh"
 
 // `define QUEUE_FORCE_MLAB 1
 // `define SYN 1

hw/rtl/VX_dmem_controller.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_dmem_controller (
 	input wire               clk,

hw/rtl/VX_execute_unit.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_execute_unit (
 	input wire            clk,

hw/rtl/VX_fetch.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_fetch (
 	input  wire              	clk,

hw/rtl/VX_front_end.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_front_end (
 	input wire 				clk,

hw/rtl/VX_gpgpu_inst.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_gpgpu_inst (
 	// Input

hw/rtl/VX_gpr.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_gpr (
 	input wire      clk,

hw/rtl/VX_gpr_stage.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_gpr_stage (
 	input wire                 clk,

hw/rtl/VX_gpr_wrapper.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_gpr_wrapper (
 	input wire                  clk,

hw/rtl/VX_icache_stage.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_icache_stage (
 	input  wire             clk,

hw/rtl/VX_inst_multiplex.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_inst_multiplex (
 	// Inputs

hw/rtl/VX_lsu.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_lsu (
 	input wire              clk,

hw/rtl/VX_lsu_addr_gen.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_lsu_addr_gen (
 	input  wire[`NUM_THREADS-1:0][31:0] base_address,

hw/rtl/VX_scheduler.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_scheduler (
 	input wire              clk,

hw/rtl/VX_warp.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 
 module VX_warp (

hw/rtl/VX_warp_scheduler.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_warp_scheduler (
 	input wire           clk,    // Clock

hw/rtl/VX_writeback.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_writeback (
 	input wire 			clk,

hw/rtl/Vortex.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 `include "VX_cache_config.vh"
 
 module Vortex #( 

hw/rtl/Vortex_Cluster.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 `include "VX_cache_config.vh"
 
 module Vortex_Cluster #(

hw/rtl/Vortex_Socket.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 `include "VX_cache_config.vh"
 
 module Vortex_Socket (

hw/rtl/byte_enabled_simple_dual_port_ram.v

@@ -1,5 +1,5 @@
 
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module byte_enabled_simple_dual_port_ram
 (

hw/rtl/cache/VX_bank.v

@@ -1,5 +1,5 @@
 `include "VX_cache_config.vh"
-`include "VX_define.v"
+`include "VX_define.vh"
 module VX_bank #(
 	// Size of cache in bytes
 	parameter CACHE_SIZE_BYTES              = 1024, 

hw/rtl/cache/VX_cache_config.vh

@@ -1,7 +1,7 @@
 `ifndef VX_CACHE_CONFIG
 `define VX_CACHE_CONFIG
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 //                                data         tid                   rd  wb    warp_num  read write
 `define MRVQ_METADATA_SIZE      (`WORD_SIZE + `LOG2UP(NUM_REQUESTS) + 5 + 2 + (`NW_BITS) + 3 + 3)

hw/rtl/interfaces/VX_branch_response_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_BRANCH_RSP
 `define VX_BRANCH_RSP
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_branch_response_if ();
 

hw/rtl/interfaces/VX_csr_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_CSR_REQ
 `define VX_CSR_REQ
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_csr_req_if ();
 

hw/rtl/interfaces/VX_csr_wb_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_CSR_WB_REQ
 `define VX_CSR_WB_REQ
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_csr_wb_if ();
 

hw/rtl/interfaces/VX_dcache_request_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_DCACHE_REQ
 `define VX_DCACHE_REQ
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_dcache_request_if ();
 

hw/rtl/interfaces/VX_dcache_response_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_DCACHE_RSP
 `define VX_DCACHE_RSP
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_dcache_response_if ();
 

hw/rtl/interfaces/VX_dram_req_rsp_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_DRAM_REQ_RSP_INTER
 `define VX_DRAM_REQ_RSP_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_dram_req_rsp_if #(
 	parameter NUM_BANKS = 8,

hw/rtl/interfaces/VX_exec_unit_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_EXE_UNIT_REQ_INTER
 `define VX_EXE_UNIT_REQ_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_exec_unit_req_if ();
 

hw/rtl/interfaces/VX_frE_to_bckE_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_FrE_to_BE_INTER
 `define VX_FrE_to_BE_INTER
 
-`include "VX_define.v"
+`include "VX_define.vh"
 
 interface VX_frE_to_bckE_req_if ();
 

hw/rtl/interfaces/VX_gpr_data_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_gpr_data_INTER
 `define VX_gpr_data_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_gpr_data_if ();
 

hw/rtl/interfaces/VX_gpr_jal_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_GPR_JAL_INTER
 `define VX_GPR_JAL_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_gpr_jal_if ();
 

hw/rtl/interfaces/VX_gpr_read_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_GPR_READ
 `define VX_GPR_READ
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_gpr_read_if ();
 

hw/rtl/interfaces/VX_gpu_inst_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_GPU_INST_REQ_IN
 `define VX_GPU_INST_REQ_IN
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_gpu_inst_req_if();
 

hw/rtl/interfaces/VX_icache_request_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_ICACHE_REQ
 `define VX_ICACHE_REQ
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_icache_request_if ();
 

hw/rtl/interfaces/VX_icache_response_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_ICACHE_RSP
 `define VX_ICACHE_RSP
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_icache_response_if ();
 

hw/rtl/interfaces/VX_inst_exec_wb_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_EXEC_UNIT_WB_INST_INTER
 `define VX_EXEC_UNIT_WB_INST_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_inst_exec_wb_if ();
 

hw/rtl/interfaces/VX_inst_mem_wb_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_MEM_WB_INST_INTER
 `define VX_MEM_WB_INST_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_inst_mem_wb_if ();
 

hw/rtl/interfaces/VX_inst_meta_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_F_D_INTER
 `define VX_F_D_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_inst_meta_if ();
 

hw/rtl/interfaces/VX_jal_response_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_JAL_RSP
 `define VX_JAL_RSP
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_jal_response_if ();
 

hw/rtl/interfaces/VX_join_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_JOIN_INTER
 `define VX_JOIN_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_join_if ();
 

hw/rtl/interfaces/VX_lsu_req_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_LSU_REQ_INTER
 `define VX_LSU_REQ_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_lsu_req_if ();
 

hw/rtl/interfaces/VX_mem_req_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_MEM_REQ_IN
 `define VX_MEM_REQ_IN
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_mem_req_if ();
 

hw/rtl/interfaces/VX_mw_wb_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_MW_WB_INTER
 `define VX_MW_WB_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_mw_wb_if ();
 

hw/rtl/interfaces/VX_warp_ctl_if.v

@@ -2,7 +2,7 @@
 `ifndef VX_WARP_CTL_INTER
 `define VX_WARP_CTL_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_warp_ctl_if ();
 

hw/rtl/interfaces/VX_wb_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_WB_INTER
 `define VX_WB_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_wb_if ();
 

hw/rtl/interfaces/VX_wstall_if.v

@@ -1,7 +1,7 @@
 `ifndef VX_WSTALL_INTER
 `define VX_WSTALL_INTER
 
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 interface VX_wstall_if();
 

hw/rtl/libs/VX_divide.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_divide #(
     parameter WIDTHN=1,

hw/rtl/libs/VX_generic_priority_encoder.v

@@ -1,7 +1,7 @@
 `ifndef VX_GENERIC_PRIORITY_ENCODER
 `define VX_GENERIC_PRIORITY_ENCODER
 
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_generic_priority_encoder
   #(

hw/rtl/libs/VX_generic_queue.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_generic_queue #(
     parameter DATAW,

hw/rtl/libs/VX_generic_register.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_generic_register #( 
 	parameter N, 

hw/rtl/libs/VX_mult.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_mult #(
     parameter WIDTHA=1,

hw/rtl/libs/VX_priority_encoder.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module VX_priority_encoder (
     input  wire[`NUM_WARPS-1:0] valids,

hw/rtl/libs/VX_priority_encoder_w_mask.v

@@ -1,4 +1,4 @@
-`include "VX_define.v"
+`include "VX_define.vh"
 module VX_priority_encoder_w_mask #(
 	parameter N = 10
 )  (

hw/rtl/pipe_regs/VX_d_e_reg.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 module VX_d_e_reg (
 	input wire        		clk,

hw/rtl/pipe_regs/VX_f_d_reg.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 module VX_f_d_reg (
 	input wire		clk,

hw/rtl/pipe_regs/VX_i_d_reg.v

@@ -1,4 +1,4 @@
-`include "../VX_define.v"
+`include "../VX_define.vh"
 
 module VX_i_d_reg (
 	input wire          clk,

hw/scripts/gen_config.py

@@ -61,7 +61,7 @@ translation_rules = [
     (re.compile(r'^( *)`ifndef ([^ ]+)$'), r'\1#ifndef \2'),
     (re.compile(r'^( *)`define ([^ ]+)$'), r'\1#define \2'),
     # (re.compile(r'^( *)`include "\./VX_define_synth\.v"$'), r'\1#include "VX_define_synth.h"'),
-    (re.compile(r'^( *)`include "VX_user_config\.v"$'), r''),
+    (re.compile(r'^( *)`include "VX_user_config\.vh"$'), r''),
     (re.compile(r'^( *)`define ([^ ]+) (.+)$'), r'\1#define \2 \3'),
     (re.compile(r'^( *)`endif$'), r'\1#endif'),
     (re.compile(r'^( *)// (.*)$'), r'\1// \2'),
@@ -93,9 +93,9 @@ if args.outc != 'none':
 // auto-generated by gen_config.py. DO NOT EDIT
 // Generated at {date}
 
-// Translated from VX_config.v:
+// Translated from VX_config.vh:
 '''[1:].format(date=datetime.now()), file=f)
-        with open(path.join(script_dir, '../rtl/VX_config.v'), 'r') as r:
+        with open(path.join(script_dir, '../rtl/VX_config.vh'), 'r') as r:
             for line in r:
                 if in_expansion:
                     f.write(post_process_line(line))

hw/syn/synopsys/esyn.tcl

@@ -4,9 +4,9 @@ set link_library		[concat ./NanGate_15nm_OCL.db]
 set symbol_library		{}
 set target_library		[concat ./NanGate_15nm_OCL.db]
 
-set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_config.v VX_user_config.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
+set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_config.vh VX_user_config.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
 					]
-# set verilog_files 	[ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
+# set verilog_files 	[ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
 # 					]
 
 set top_level Vortex

hw/syn/synopsys/fsyn.tcl

@@ -2,9 +2,9 @@ set search_path			[concat ../../models/memory/cln28hpm/rf2_128x128_wm1 ../../mod
 set link_library		[concat NanGate_15nm_OCL.db]
 set symbol_library		{}
 set target_library		[concat NanGate_15nm_OCL.db]
-set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v \
+set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_bank_valid.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v rf2_128x128_wm1.v \
 					]
-# set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \
+# set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \
 # 					]
 
 set top_level Vortex

hw/syn/synopsys/syn.tcl

@@ -3,9 +3,9 @@ set link_library		[concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_
 set symbol_library		{}
 set target_library		[concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]
 
-set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
+set verilog_files 	[ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_cache_data_per_index.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
 					]
-# set verilog_files 	[ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
+# set verilog_files 	[ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v  VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.vh VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
 # 					]
 
 set top_level Vortex

simX/cache_simX.v

@@ -1,5 +1,5 @@
 
-`include "VX_define.v"
+`include "VX_define.vh"
 
 module cache_simX (
 	input       wire clk,    // Clock