125 lines
3.1 KiB
Verilog
125 lines
3.1 KiB
Verilog
`include "VX_define.vh"
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module VX_back_end #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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input wire schedule_delay,
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VX_gpu_dcache_rsp_if dcache_rsp_if,
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VX_gpu_dcache_req_if dcache_req_if,
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output wire mem_delay_o,
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output wire exec_delay_o,
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output wire gpr_stage_delay,
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VX_jal_response_if jal_rsp_if,
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VX_branch_response_if branch_rsp_if,
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VX_frE_to_bckE_req_if bckE_req_if,
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VX_wb_if writeback_if,
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VX_warp_ctl_if warp_ctl_if
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);
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VX_wb_if writeback_temp_if();
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assign writeback_if.wb = writeback_temp_if.wb;
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assign writeback_if.rd = writeback_temp_if.rd;
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assign writeback_if.write_data = writeback_temp_if.write_data;
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assign writeback_if.wb_valid = writeback_temp_if.wb_valid;
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assign writeback_if.wb_warp_num = writeback_temp_if.wb_warp_num;
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assign writeback_if.wb_pc = writeback_temp_if.wb_pc;
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// assign VX_writeback_if(writeback_temp_if);
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wire no_slot_mem;
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wire no_slot_exec;
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// LSU input + output
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VX_lsu_req_if lsu_req_if();
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VX_inst_mem_wb_if mem_wb_if();
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// Exec unit input + output
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VX_exec_unit_req_if exec_unit_req_if();
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VX_inst_exec_wb_if inst_exec_wb_if();
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// GPU unit input
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VX_gpu_inst_req_if gpu_inst_req_if();
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// CSR unit inputs
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VX_csr_req_if csr_req_if();
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VX_csr_wb_if csr_wb_if();
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wire no_slot_csr;
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wire stall_gpr_csr;
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VX_gpr_stage gpr_stage (
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.writeback_if (writeback_temp_if),
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.bckE_req_if (bckE_req_if),
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// New
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.exec_unit_req_if (exec_unit_req_if),
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.lsu_req_if (lsu_req_if),
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.gpu_inst_req_if (gpu_inst_req_if),
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.csr_req_if (csr_req_if),
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.stall_gpr_csr (stall_gpr_csr),
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// End new
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.memory_delay (mem_delay_o),
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.exec_delay (exec_delay_o),
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.gpr_stage_delay (gpr_stage_delay)
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);
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VX_lsu load_store_unit (
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.clk (clk),
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.reset (reset),
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.lsu_req_if (lsu_req_if),
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.mem_wb_if (mem_wb_if),
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.dcache_rsp_if (dcache_rsp_if),
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.dcache_req_if (dcache_req_if),
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.delay_o (mem_delay_o),
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.no_slot_mem_i (no_slot_mem)
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);
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VX_execute_unit execUnit (
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.clk (clk),
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.reset (reset),
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.exec_unit_req_if(exec_unit_req_if),
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.inst_exec_wb_if (inst_exec_wb_if),
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.jal_rsp_if (jal_rsp_if),
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.branch_rsp_if (branch_rsp_if),
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.delay_o (exec_delay_o),
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.no_slot_exec_i (no_slot_exec)
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);
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VX_gpgpu_inst gpgpu_inst (
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.gpu_inst_req_if(gpu_inst_req_if),
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.warp_ctl_if (warp_ctl_if)
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);
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VX_csr_pipe #(
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.CORE_ID(CORE_ID)
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) csr_pipe (
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.clk (clk),
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.reset (reset),
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.no_slot_csr (no_slot_csr),
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.csr_req_if (csr_req_if),
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.writeback_if(writeback_temp_if),
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.csr_wb_if (csr_wb_if),
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.stall_gpr_csr(stall_gpr_csr)
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);
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VX_writeback wb (
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.clk (clk),
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.reset (reset),
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.mem_wb_if (mem_wb_if),
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.inst_exec_wb_if (inst_exec_wb_if),
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.csr_wb_if (csr_wb_if),
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.writeback_if (writeback_temp_if),
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.no_slot_mem_o (no_slot_mem),
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.no_slot_exec_o (no_slot_exec),
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.no_slot_csr_o (no_slot_csr)
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);
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endmodule |