49 lines
1.0 KiB
Verilog
49 lines
1.0 KiB
Verilog
`ifndef VX_EXE_UNIT_REQ_INTER
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`define VX_EXE_UNIT_REQ_INTER
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`include "../VX_define.vh"
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interface VX_exec_unit_req_if ();
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// Meta
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wire [`NUM_THREADS-1:0] valid;
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wire [`NW_BITS-1:0] warp_num;
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wire [31:0] curr_PC;
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wire [31:0] PC_next;
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// Write Back Info
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wire [4:0] rd;
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wire [1:0] wb;
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// Data and alu op
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wire [`NUM_THREADS-1:0][31:0] a_reg_data;
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wire [`NUM_THREADS-1:0][31:0] b_reg_data;
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wire [4:0] alu_op;
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wire [4:0] rs1;
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wire [4:0] rs2;
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wire rs2_src;
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wire [31:0] itype_immed;
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wire [19:0] upper_immed;
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// Branch type
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wire [2:0] branch_type;
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// Jal info
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wire jalQual;
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wire jal;
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wire [31:0] jal_offset;
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`IGNORE_WARNINGS_BEGIN
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wire ebreak;
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wire wspawn;
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`IGNORE_WARNINGS_END
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// CSR info
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wire is_csr;
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wire [11:0] csr_address;
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wire csr_immed;
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wire [31:0] csr_mask;
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endinterface
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`endif |