95 lines
2.7 KiB
Verilog
95 lines
2.7 KiB
Verilog
`include "VX_define.vh"
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module VX_writeback (
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input wire clk,
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input wire reset,
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// Mem WB info
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VX_inst_mem_wb_if mem_wb_if,
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// EXEC Unit WB info
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VX_inst_exec_wb_if inst_exec_wb_if,
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// CSR Unit WB info
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VX_csr_wb_if csr_wb_if,
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// Actual WB to GPR
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VX_wb_if writeback_if,
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output wire no_slot_mem_o,
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output wire no_slot_exec_o,
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output wire no_slot_csr_o
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);
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VX_wb_if writeback_tempp_if();
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wire exec_wb = (inst_exec_wb_if.wb != 0) && (|inst_exec_wb_if.wb_valid);
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wire mem_wb = (mem_wb_if.wb != 0) && (|mem_wb_if.wb_valid);
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wire csr_wb = (csr_wb_if.wb != 0) && (|csr_wb_if.valid);
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assign no_slot_mem_o = mem_wb && (exec_wb || csr_wb);
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assign no_slot_csr_o = csr_wb && (exec_wb);
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assign no_slot_exec_o = 0;
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assign writeback_tempp_if.write_data = exec_wb ? inst_exec_wb_if.alu_result :
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csr_wb ? csr_wb_if.csr_result :
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mem_wb ? mem_wb_if.loaded_data :
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0;
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assign writeback_tempp_if.wb_valid = exec_wb ? inst_exec_wb_if.wb_valid :
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csr_wb ? csr_wb_if.valid :
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mem_wb ? mem_wb_if.wb_valid :
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0;
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assign writeback_tempp_if.rd = exec_wb ? inst_exec_wb_if.rd :
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csr_wb ? csr_wb_if.rd :
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mem_wb ? mem_wb_if.rd :
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0;
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assign writeback_tempp_if.wb = exec_wb ? inst_exec_wb_if.wb :
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csr_wb ? csr_wb_if.wb :
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mem_wb ? mem_wb_if.wb :
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0;
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assign writeback_tempp_if.wb_warp_num = exec_wb ? inst_exec_wb_if.wb_warp_num :
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csr_wb ? csr_wb_if.warp_num :
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mem_wb ? mem_wb_if.wb_warp_num :
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0;
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assign writeback_tempp_if.wb_pc = exec_wb ? inst_exec_wb_if.exec_wb_pc :
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csr_wb ? 32'hdeadbeef :
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mem_wb ? mem_wb_if.mem_wb_pc :
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32'hdeadbeef;
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wire zero = 0;
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wire[`NUM_THREADS-1:0][31:0] use_wb_data;
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VX_generic_register #(.N(39 + `NW_BITS-1 + 1 + `NUM_THREADS*33)) wb_register(
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.clk (clk),
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.reset(reset),
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.stall(zero),
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.flush(zero),
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.in ({writeback_tempp_if.write_data, writeback_tempp_if.wb_valid, writeback_tempp_if.rd, writeback_tempp_if.wb, writeback_tempp_if.wb_warp_num, writeback_tempp_if.wb_pc}),
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.out ({use_wb_data , writeback_if.wb_valid, writeback_if.rd, writeback_if.wb, writeback_if.wb_warp_num, writeback_if.wb_pc})
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);
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reg[31:0] last_data_wb /* verilator public */ ;
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always @(posedge clk) begin
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if ((|writeback_if.wb_valid) && (writeback_if.wb != 0) && (writeback_if.rd == 28)) begin
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last_data_wb <= use_wb_data[0];
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end
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end
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assign writeback_if.write_data = use_wb_data;
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endmodule : VX_writeback
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