wu-arch/chipyard
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ebfa545344fcfea8bf17f598575b7a581c04d333
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47 Commits

Author SHA1 Message Date
Jerry Zhao
ebfa545344 Generator unification 2020-02-13 12:33:28 -08:00
Jerry Zhao
49dbe8daba Rename top-level example package to chipyard 
* FireChip now directly uses the Chipyard Top
 2020-02-13 12:33:04 -08:00
Jerry Zhao
05f17f5b99 [tracegen] Add tracegen support for the BOOM L1D (#362) 
* [tracegen] Add tracegen support for the BOOM L1D

* [tracegen] Split up BOOM Tracegen mixin and shim.

* [ci] Fix tracegen hash for testing
 2020-01-23 16:01:32 -08:00
Abraham Gonzalez
9e2726a251 Add UART and UARTAdapter to all configs (#348) 
* [uart] add uart adapter | add uart + adapter to all configs

* [uart] bump testchipip | add small documentation in generators section
 2020-01-16 11:33:46 -08:00
Howard Mao
cc564e0bfe add example NIC configuration 2019-12-16 09:02:01 -08:00
alonamid
56770a1a4c Gemmini Integration (#356) 
* gemmini submodule

* fix build.sbt

* firechip gemmini config

* bump gemmini

* bump gemmini

* bump gemmini

* fix hwacha typo

* start gemmini docs

* bump gemmini

* gemmini docs

* Update Gemmini RST. Add quick-build instructions to Gemmini RST

* start gemmini CI

* bump gemmini

* gemmini CI fixes

* bump gemmini

* fix simulator name in gemmini CI

* cleanup gemmini CI

* bump esp-isa-sim to include gemmini

* update gemmini docs

* [ci skip] fix gemmini docs typos

* Update Gemmini.rst

Add instructions on building Gemmini programs, or writing your own programs.

* Changed order of VCS and Verilator in Gemmini docs

* Remove "make your own tests" from Gemmini README

* bump gemmini

* try to fix midasexamples CI
 2019-12-14 01:36:42 -08:00
Colin Schmidt
86a473dbf6 Bump all submodules for chisel 3.2.0 and rocket-chip august-2019 (#358) 
* Bump all submodules for chisel 3.2.0 and rocket-chip august-2019

* Fix subprojects that aren't tested from normal sims

* Fix firechip for chisel 3.2.0 and rc bump

* Bump boom for bug fix rebase

* [sbt] Don't rely on target-rtl symlink when FireSim is top [no ci]

* Bump boom for rc bump fix to bug fix

* Bump FireSim for CI check

* Bump FireSim

* Bump submodules after merge
 2019-12-12 13:39:09 -08:00
Albert Magyar
0d5bcf9c0d Add FireChip target with Verilog blackbox (#297) 
Co-Authored-By: Abraham Gonzalez <abe.j.gonza@gmail.com>
 2019-10-16 14:31:58 -07:00
Abraham Gonzalez
61d03fe37d update build.sbt for sha3 to build midastargetutils | have midas printf parameterized in sha3 2019-10-10 00:46:04 +00:00
David Biancolin
53f58f6baa Support serializable endpoints; Golden Gate stage 2019-10-04 14:54:26 -07:00
Albert Ou
d1e3cc558b firechip: Add FireSimRocketChipSha3L2Config 2019-10-04 01:09:53 +00:00
Albert Magyar
c2ce173195 Add Verilog MMIO GCD peripheral example 2019-09-26 01:47:31 -07:00
David Biancolin
95ae46f4f2 [sbt] Use tools/chisel3 not rocketchip/chisel3 2019-09-12 20:32:33 -07:00
David Biancolin
16cc565238 [sbt] Purge berkeley library dependencies from all subprojects 2019-09-12 20:32:26 -07:00
David Biancolin
173743be6d [sbt] Remove the firrtl subproject 2019-09-12 15:41:50 -07:00
Howard Mao
34612e559c clean up dependencies 2019-09-12 00:19:55 +08:00
Howard Mao
622e6def6a chisel-testers is dependency of tapeout 2019-09-12 00:19:55 +08:00
Howard Mao
2eeda43b93 make firrtl-interpreter a submodule instead of depending on external snapshot 2019-09-12 00:19:55 +08:00
Colin Schmidt
5790bbc21b Merge remote-tracking branch 'origin/dev' into dev-sha3 2019-09-01 07:26:44 -07:00
Howard Mao
6a3212c6d7 add tracegen project 2019-08-30 11:38:07 -07:00
Colin Schmidt
a494f88af0 Add sha3 repo and config, bump tools for xcustom fix 2019-08-25 08:22:41 -07:00
Howard Mao
72adc6981c fix firesim test suite generation 2019-08-21 22:10:39 -07:00
Paul Rigge
ee75c03875 Add dsptools. 2019-08-02 15:09:22 -07:00
Howard Mao
65df55cf9d add InclusiveCache 2019-07-02 16:58:08 -07:00
David Biancolin
1f48e33be5 Bump FireSim, and add back the firrtl intrp lib dep 2019-06-28 19:16:34 +00:00
David Biancolin
f4fb0c42b1 Fix a number of build.sbt related problems 2019-05-29 22:26:04 +00:00
David Biancolin
a53abf1856 Bring up FireSim tests 2019-05-28 22:51:39 +00:00
David Biancolin
2a58f387ed Fix some test suite handling 2019-05-28 01:50:39 +00:00
David Biancolin
c0d4e848ba WIP 2019-05-27 22:53:05 +00:00
Jerry Zhao
01067df07e Update build.sbt with correct locations of example/utilities 2019-05-10 21:09:00 -07:00
Jerry Zhao
17bc3bf60d Decouple SUB_PROJECT builds from example 2019-05-10 02:40:16 -07:00
Jerry Zhao
e0d1ba285d Add Hwacha config to example project 2019-04-23 16:20:23 -07:00
abejgonzalez
862c217ff4 allow rocket builds | asm tests pass 2019-04-23 11:50:36 -07:00
abejgonzalez
c0b0e293c5 removed boom package and combined into example | removed example from naming | split generator file 2019-04-20 21:18:20 -07:00
abejgonzalez
e9ed53424b add sifive blocks | add rebar configs for boom 2019-04-19 21:06:32 -07:00
abejgonzalez
eec137e1ee make tapeout depend on testchipip for resources 2019-04-18 14:38:57 -07:00
abejgonzalez
7faaa56f34 revert condDependsOn | put new firrtl jar into rocket 2019-04-18 11:39:19 -07:00
abejgonzalez
adb8897e35 add firrtl dependency to build.sbt | point to different firrtl jar | a bunch of sbt plugins 2019-04-17 23:11:14 -07:00
abejgonzalez
68b2da6b3a update boom | match build.sbt 2019-04-17 16:06:42 -07:00
abejgonzalez
d80acd8cf8 added boom and torture | added csmith 2019-04-15 10:17:42 -07:00
alonamid
2def0dfea7 change dir structure 2019-03-12 14:30:38 -07:00
Paul Rigge
ddf3159d61 Bump rocket, make possible to use published deps (#47) 
* Use published rocketchip

* Simulator works!

* Gitignore was masking csrc

* Fix broken submodules

* Update gitignore

* Fix things up

* Some more cleanup

* Clean up so that using maven works

* Incorporate feedback

* Oops

* Add workaround for some of csrc

* Forgot dtm and jtag

* Make name better and add comment

* Extraneous comment

* Fix includes.

After running a clean build, I realized old build state was masking this
problem. verisim/csrc needs to be in the include path until we find a more
permanent solution to our problem.

* Add target to generate verilator-specific files.

* Ignore DS_Store

* Generate bootrom from testchipip

* Oops

* Add extraneous rocket-dsptools reference
 2019-03-06 18:22:21 -08:00
John Wright
acd76e5410 Adding barstools to separate the top from harness and to generate the 
memories as external modules, which makes VLSI flows easier to plug in.
 2019-02-13 21:13:08 -08:00
Albert Ou
220aeea4c8 Bump rocket-chip 
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
 2018-09-29 13:30:07 -07:00
Howard Mao
a3684d01dd use build.sbt instead of jar files to collect packages 2018-05-03 17:09:59 -07:00
Howard Mao
28539dc562 bump rocket-chip to March commit 2018-04-16 19:33:51 -07:00
Howard Mao
7074420aba initial commit 2016-10-21 16:03:26 -07:00