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Add FireChip target with Verilog blackbox (#297)

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Co-Authored-By: Abraham Gonzalez <abe.j.gonza@gmail.com>
This commit is contained in:
Albert Magyar
2019-10-16 14:31:58 -07:00
committed by GitHub
parent 701129fb62
commit 0d5bcf9c0d
2 changed files with 13 additions and 1 deletions
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build.sbt
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@@ -189,7 +189,7 @@ lazy val midas = ProjectRef(firesimDir, "midas")
lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
lazy val firechip = (project in file("generators/firechip"))
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.dependsOn(example, icenet, testchipip, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.settings(
commonSettings,
testGrouping in Test := isolateAllTests( (definedTests in Test).value )