add example NIC configuration

build.sbt

@@ -123,7 +123,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
   .settings(commonSettings)
 
 lazy val example = conditionalDependsOn(project in file("generators/example"))
-  .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini)
+  .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet)
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))

generators/example/src/main/scala/BoomConfigs.scala

@@ -67,4 +67,11 @@ class HwachaLargeBoomConfig extends Config(
   new boom.common.WithNBoomCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 
-
+class LoopbackNICBoomConfig extends Config(
+  new WithIceNIC ++
+  new WithLoopbackNICTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithLargeBooms ++                         // 3-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)

generators/example/src/main/scala/ConfigMixins.scala

@@ -18,6 +18,8 @@ import hwacha.{Hwacha}
 
 import sifive.blocks.devices.gpio._
 
+import icenet.{NICKey, NICConfig}
+
 /**
  * TODO: Why do we need this?
  */
@@ -213,3 +215,18 @@ class WithControlCore extends Config((site, here, up) => {
     )
   case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
 })
+
+class WithIceNIC(inBufFlits: Int = 1800, usePauser: Boolean = false)
+    extends Config((site, here, up) => {
+  case NICKey => NICConfig(
+    inBufFlits = inBufFlits,
+    usePauser = usePauser)
+})
+
+class WithLoopbackNICTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithIceNIC()(p)).module)
+    top.connectNicLoopback()
+    top
+  }
+})

generators/example/src/main/scala/RocketConfigs.scala

@@ -151,3 +151,11 @@ class InitZeroRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
 // DOC include end: InitZeroRocketConfig
+
+class LoopbackNICRocketConfig extends Config(
+  new WithIceNIC ++
+  new WithLoopbackNICTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)

generators/example/src/main/scala/Top.scala

@@ -14,6 +14,8 @@ import utilities.{System, SystemModule}
 
 import sifive.blocks.devices.gpio._
 
+import icenet.{HasPeripheryIceNIC, HasPeripheryIceNICModuleImp}
+
 // ------------------------------------
 // BOOM and/or Rocket Top Level Systems
 // ------------------------------------
@@ -101,3 +103,12 @@ class TopWithInitZero(implicit p: Parameters) extends Top
 class TopWithInitZeroModuleImp(l: TopWithInitZero) extends TopModule(l)
   with HasPeripheryInitZeroModuleImp
 // DOC include end: TopWithInitZero
+
+class TopWithIceNIC(implicit p: Parameters) extends Top
+    with HasPeripheryIceNIC {
+  override lazy val module = new TopWithIceNICModule(this)
+}
+
+class TopWithIceNICModule(outer: TopWithIceNIC)
+  extends TopModule(outer)
+  with HasPeripheryIceNICModuleImp