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87 Commits

Author SHA1 Message Date
chick
a3711c4e19 Remove fully commented out original file Generate.scala 2021-02-22 11:39:47 -08:00
chick
8a93d8b2d7 Ignore GenerateTopAndHarness test for now 2021-02-19 14:48:48 -08:00
chick
bbc8800840 Get topAnnos into the mix 2021-02-16 16:29:41 -08:00
chick
7c2d7abbe1 Add in missing transforms 2021-02-16 14:43:58 -08:00
chick
055800898d - Don't carry over OutputFileAnnotaton to the harness phase of GenerateTopAndHarness 2021-02-14 16:18:04 -08:00
chick
5616b9d68f - remove unused harnessTransforms 
-
 2021-02-14 13:25:16 -08:00
chick
f37385ca58 Merge branch 'master' into fix-deprecations-3 2021-02-10 11:36:23 -08:00
chick
e650d5ba22 - changed directory path to iocells to use directories rather than dotted name 
- Changed packages in tapeout/transforms/utils/*.scala to be in their own package `utils`
 2021-02-09 14:12:57 -08:00
chick
afcdcc6c2d Modernize deprecated Chisel/Firrtl constructs 
- Build out a stage for tapeout
  - Refactor annotation construction
  - Create a CLI handler
  - create a TapeOutStage
- Remove outputForm reference from EnumerateModules
- New GenerateTopAndHarness is fresh implmentation of Generate.scala
- GenerateTopSpec is a work in progress
 2021-02-09 14:04:24 -08:00
chick
d9d9d0fbb5 Move to scalatest 3.2 
Requires updating to AnyFlatSpec where used
And different import for Matchers
 2021-02-03 21:03:22 -08:00
chick
caa1467d87 Reformat all scala files in tapeout 
- Mostly this reformat comments and large argument lists to classes and methods
 2021-02-03 17:51:30 -08:00
chick
19e51f3df5 Make the directory structure match the packages 
All tests run as they did prior to the changes
 2021-02-03 17:46:12 -08:00
abejgonzalez
689ebdc06e Add invalidates=false to RetimeTransform 2020-12-11 15:01:17 -08:00
abejgonzalez
26dce446ea Generate LowFirrtl for Retime tests 2020-12-11 14:51:43 -08:00
abejgonzalez
62f311654a Fix ResetInv test 2020-12-11 14:11:08 -08:00
abejgonzalez
fa699af026 Add missing dependency to put AvoidExtModuleCollisions before ReplSeqMem 2020-11-27 17:34:16 -08:00
abejgonzalez
9be550e23d Bump to new dep. API | Automatically avoid renaming ExtMod's and circuit top mod 2020-11-25 20:50:54 -08:00
abejgonzalez
845af06b15 Merge remote-tracking branch 'origin/master' into firrtl-1.4-remove-clk-stuff 2020-11-19 16:59:49 -08:00
chick
a1dfd4f774 Remove all of the PadStuff 2020-09-30 15:04:56 -07:00
chick
1a82c082b3 - Make transfrorms run in as close to same order as before 
- Fix parsing of PadPlacement JSON
 2020-09-29 10:11:46 -07:00
chick
f51156bf1f - Fixed ResetNSpec 2020-09-28 15:34:36 -07:00
chick
0430403920 - Simplest way to make custom transforms run in same place as they did prior to Dependency API 2020-09-28 15:20:42 -07:00
Jerry Zhao
847f72eca0 Support plusarg_reader blackbox in the harness 2020-09-14 19:39:44 -07:00
chick
d06d8cc16c - FoundryPadsYaml would not parse yaml 
- Made separate case class for data
  - Now parses
  - Fails later with UnknownType in firrt compiler
- Fixed similar parsing problem with PadPlacement
 2020-09-14 09:32:18 -07:00
chick
67de39e957 Refactor tapeout for Chisel 3.4, Firrtl 1.4 
- Remove clk package based on discussion with Colin
- Annotations need to be refactored to using latest API
  - Generally that involves making annos generated by a anonymous ChiselAnnotation
  - The chisel annotations will use RunFirrtlTransform to queue up its associated transform
  - Chisel annotation provieds toFirrtl to generate Firrtl form of annotation
- Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated
- Have transforms use with DependencyAPIMigration to avoid deprecated `form`s
- Added some 'see License comments
- TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it.
  - Added some tests for annotation serialization here
 2020-09-11 17:06:19 -07:00
chick
e4cd2b01fe This is mess clean it up 2020-09-10 14:35:10 -07:00
Albert Magyar
acda0a3490 Changes to tapeout transforms to support FIRRTL 1.3 2020-05-13 10:34:57 -07:00
Colin Schmidt
db0efd38fc Fix CI tests 2020-02-19 17:23:10 -08:00
Colin Schmidt
7de4c478c3 Update to chisel 3.2.x 2020-02-18 14:56:17 -08:00
Colin Schmidt
e0081208b9 Updates for rocket-chip bump 2019-12-06 15:39:14 -08:00
Colin Schmidt
e4cce07c78 Fix issues after chisel update for august 2019 2019-12-06 15:38:19 -08:00
Abraham Gonzalez
3bba55ccc8 Merge pull request #68 from ucb-bar/print-firrtl-exception 
Print the firrtl exception if we get one
 2019-11-07 13:39:12 -08:00
Abraham Gonzalez
1e114d0355 Match inner variables 2019-11-07 10:17:24 -08:00
Colin Schmidt
c1004790cc Use x instead of e to match other case 2019-10-28 07:33:04 -07:00
Colin Schmidt
c96a5e5f44 Print the firrtl exception if we get one 
Fixes #67
 2019-10-24 14:55:03 -07:00
Albert Magyar
76ccb75b00 Filter out all deleted annotations 2019-08-19 09:08:30 -07:00
Abraham Gonzalez
76f6c8adb2 remove large annotations 2019-08-17 10:35:41 -07:00
Albert Magyar
26096e07f6 Coordinate Top and Harness generation (#63) 
* Coordinate Top and Harness generation

* Update to use .f filename override annotations

* Move top generation to def to help GC
 2019-07-30 22:42:05 -07:00
Albert Magyar
e3c822709b Filter all EmittedAnnotations from JSON emission (#64) 
* Filter all EmittedAnnotations from JSON emission

* Filter more annotations
 2019-07-29 20:39:07 -07:00
Colin Schmidt
c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
John Wright
e548210ef4 Add options to emit top/harness firrtl and annotations (#54) 2019-03-29 13:55:18 -07:00
Colin Schmidt
8f7af5b0bf Fix annos (#53) 
* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
 2019-03-27 17:20:41 -07:00
Colin Schmidt
fdad525007 HighForm has whens so we need to check for instances there (#49) 
Fixes a bug
 2019-03-18 11:25:58 -07:00
Colin Schmidt
6cdf978a6d Fix forms of passes to happen before replseqmem 
This ensures the conf file doesn't have any testharness
memories, which are too big and break downstream tools
 2019-03-18 07:25:04 -07:00
Colin Schmidt
a10a6cca35 Add SimDTM to list of extmodules 2019-03-01 18:52:41 -08:00
John Wright
1f58ea1e14 Style/Comments from review of #35 2019-02-13 10:15:51 -08:00
John Wright
79b8fd324b This compiles and works correctly, but is kind of hacky, and will break as soon as any additional external/blackbox modules are added to the test harness. The test harness should detect external modules and not rename them instead of what is happening here. 2019-02-13 10:15:51 -08:00
John Wright
c8efc5e88b Refactor the harness generation; use upstream arguments and passes where appropriate 2019-02-13 10:15:51 -08:00
Paul Rigge
22e6d9c5d4 Fix repl-seq-mem 2019-02-13 10:15:51 -08:00
Paul Rigge
7bbf7f00f6 Run transforms in slightly different order 
Also, don't rename TestHarness.
 2019-02-13 10:15:51 -08:00