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- Fixed ResetNSpec

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chick
2020-09-28 15:34:36 -07:00
parent 0430403920
commit f51156bf1f
2 changed files with 7 additions and 4 deletions
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3
tapeout/src/main/scala/transforms/ResetInverter.scala
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@@ -24,7 +24,8 @@ object ResetN extends Pass {
"Can only invert reset on a module with reset!")
// Rename "reset" to "reset_n"
val portsx = mod.ports map {
case Port(info, "reset", Input, Bool) => Port(info, "reset_n", Input, Bool)
case Port(info, "reset", Input, Bool) =>
Port(info, "reset_n", Input, Bool)
case other => other
}
val newReset = DefNode(NoInfo, "reset", DoPrim(Not, Seq(Reference("reset_n", Bool)), Seq.empty, Bool))

8
tapeout/src/test/scala/transforms/ResetInverterSpec.scala
View File

@@ -19,13 +19,15 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
}
class ResetNSpec extends FreeSpec with Matchers {
"Inverting reset needs to be done throughout module" in {
val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array())
"Inverting reset needs to be done throughout module in Chirrtl" in {
val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--no-run-firrtl"))
chirrtl should include("input reset :")
(chirrtl should not).include("input reset_n :")
(chirrtl should not).include("node reset = not(reset_n)")
}
val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted, Array("-X", "low"))
"Inverting reset needs to be done throughout module when generating firrtl" in {
val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted)
firrtl should include("input reset_n :")
firrtl should include("node reset = not(reset_n)")
(firrtl should not).include("input reset :")