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Fix ResetInv test

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This commit is contained in:
abejgonzalez
2020-12-11 14:11:08 -08:00
parent 15fa68b3a4
commit 62f311654a
1 changed files with 13 additions and 3 deletions
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16
tapeout/src/test/scala/transforms/ResetInverterSpec.scala
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@@ -3,7 +3,8 @@
package barstools.tapeout.transforms
import chisel3._
import chisel3.stage.ChiselStage
import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
import org.scalatest.{FreeSpec, Matchers}
class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
@@ -20,14 +21,23 @@ class ExampleModuleNeedsResetInverted extends Module with ResetInverter {
class ResetNSpec extends FreeSpec with Matchers {
"Inverting reset needs to be done throughout module in Chirrtl" in {
val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted, Array("--no-run-firrtl"))
val chirrtl = (new ChiselStage).emitChirrtl(new ExampleModuleNeedsResetInverted)
chirrtl should include("input reset :")
(chirrtl should not).include("input reset_n :")
(chirrtl should not).include("node reset = not(reset_n)")
}
"Inverting reset needs to be done throughout module when generating firrtl" in {
val firrtl = (new ChiselStage).emitFirrtl(new ExampleModuleNeedsResetInverted)
// generate low-firrtl
val firrtl = (new ChiselStage).execute(
Array("-X", "low"),
Seq(ChiselGeneratorAnnotation(() => new ExampleModuleNeedsResetInverted))
).collect {
case EmittedFirrtlCircuitAnnotation(a) => a
case EmittedFirrtlModuleAnnotation(a) => a
}.map(_.value)
.mkString("")
firrtl should include("input reset_n :")
firrtl should include("node reset = not(reset_n)")
(firrtl should not).include("input reset :")