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Author SHA1 Message Date
chick
e4cd2b01fe This is mess clean it up 2020-09-10 14:35:10 -07:00
Jerry Zhao
f791073f02 Merge pull request #85 from ucb-bar/iocells_fix 
Fix IOCells generation
 2020-07-03 12:07:35 -07:00
Jerry Zhao
aa1c90c4cc Fix IOCells generation 
* Fixes Bool wires matching both Reset and Bits
 2020-06-30 13:33:06 -07:00
Abraham Gonzalez
7e6e19b8ad Merge pull request #82 from ucb-bar/fix-output-iocell 
Fix direction of output enable in output io cell
 2020-05-29 17:23:03 -07:00
Colin Schmidt
b1c1f01c90 Fix direction of output enable in output io cell 2020-05-29 15:09:45 -07:00
Albert Magyar
c4e5f66c5e Provide MidForm circuit to MacroCompilerTransform 2020-05-13 10:34:57 -07:00
Albert Magyar
757c39ac1c Change macrocompiler to support FIRRTL 1.3 -- not backwards compatible 2020-05-13 10:34:57 -07:00
Albert Magyar
acda0a3490 Changes to tapeout transforms to support FIRRTL 1.3 2020-05-13 10:34:57 -07:00
David Biancolin
e230e8cf3f Update IOCell gen to handle abstract and async reset (#79) 2020-04-17 22:05:48 -07:00
John Wright
db6776367c Merge pull request #78 from ucb-bar/iocells 
Add IO cell models
 2020-03-31 16:32:17 -07:00
John Wright
6638f5c77e More CR feedback, fix bug introduced in previous commit 2020-03-31 13:06:01 -07:00
John Wright
c043f344b8 Code review feedback 2020-03-30 19:15:19 -07:00
John Wright
bc3f8a42b3 Forgot to update the verilog modules 2020-03-30 13:50:27 -07:00
John Wright
62df79934e Remove type casts; use a tuple match instead 2020-03-30 13:10:00 -07:00
John Wright
a6731f6a5e Rename example -> generic 2020-03-30 12:33:44 -07:00
John Wright
f6057ff947 Allow naming, make the auto-clone IO method work 2020-03-18 22:25:08 -07:00
John Wright
8a38171d18 First pass that works 2020-03-18 21:05:27 -07:00
John Wright
84c880d231 WIP; does not compile, but useful as a code review starting point 2020-03-17 14:02:11 -07:00
Colin Schmidt
63d74bc177 Merge pull request #75 from ucb-bar/bump_chisel_3.2.x 
Update to chisel 3.2.x
 2020-02-25 18:34:10 -08:00
Colin Schmidt
5fcae01825 Fix width of zeros after #74 2020-02-19 18:52:48 -08:00
Colin Schmidt
a00771d33a Merge branch 'master' into bump_chisel_3.2.x 2020-02-19 18:05:16 -08:00
Colin Schmidt
db0efd38fc Fix CI tests 2020-02-19 17:23:10 -08:00
Colin Schmidt
7de4c478c3 Update to chisel 3.2.x 2020-02-18 14:56:17 -08:00
Albert Magyar
8ca876503c Correctly specify width of default zero output value (#74) 2020-02-11 20:04:22 -07:00
Colin Schmidt
5198b3883c Merge pull request #73 from ucb-bar/rc-bump-aug-2019 
Rc bump aug 2019
 2019-12-12 13:20:53 -08:00
Colin Schmidt
e0081208b9 Updates for rocket-chip bump 2019-12-06 15:39:14 -08:00
Colin Schmidt
e4cce07c78 Fix issues after chisel update for august 2019 2019-12-06 15:38:19 -08:00
Abraham Gonzalez
3bba55ccc8 Merge pull request #68 from ucb-bar/print-firrtl-exception 
Print the firrtl exception if we get one
 2019-11-07 13:39:12 -08:00
Abraham Gonzalez
1e114d0355 Match inner variables 2019-11-07 10:17:24 -08:00
Abraham Gonzalez
7a0246ba7f Merge pull request #70 from ucb-bar/abejgonzalez-patch-1 
Fix MacroCompiler for CE-less Library Memories
 2019-11-06 23:37:20 -08:00
Abraham Gonzalez
ecc52b9b7c add test case for we bug 2019-11-05 21:29:57 -08:00
Abraham Gonzalez
4db4ebb5f5 Merge pull request #66 from ucb-bar/large-anno-remove 
Remove large annotations
 2019-11-05 17:16:03 -08:00
Abraham Gonzalez
34984802b2 enforce re is disabled when we is enabled 2019-11-05 14:16:53 -08:00
Abraham Gonzalez
46e2ecb9ae Fix MacroCompiler for CE-less Library Memories 
If a memory doesn't have a mask and doesn't have a chip enable, make sure that you use the `mem` chip enable to connect to the `we` port on the `lib` memory. Fixes a bug where the `lib` `we` signal would be tied to the `mem` `wmode` signal but then the macro would have no `en` signal connected to it.
 2019-11-05 14:04:31 -08:00
Abraham Gonzalez
8b0ef4d770 Merge pull request #69 from ucb-bar/abejgonzalez-patch-1 
Fix macrocompiler for RW mask port
 2019-11-04 13:23:05 -08:00
Abraham Gonzalez
6c59cac744 fix spacing 2019-10-28 13:47:07 -07:00
Abraham Gonzalez
be3b05a909 add test case 2019-10-28 13:45:05 -07:00
Colin Schmidt
c1004790cc Use x instead of e to match other case 2019-10-28 07:33:04 -07:00
Abraham Gonzalez
7f0828cb30 Fix macrocompiler for RW mask port 2019-10-25 20:42:55 -07:00
Colin Schmidt
c96a5e5f44 Print the firrtl exception if we get one 
Fixes #67
 2019-10-24 14:55:03 -07:00
Albert Magyar
76ccb75b00 Filter out all deleted annotations 2019-08-19 09:08:30 -07:00
Abraham Gonzalez
76f6c8adb2 remove large annotations 2019-08-17 10:35:41 -07:00
Albert Magyar
26096e07f6 Coordinate Top and Harness generation (#63) 
* Coordinate Top and Harness generation

* Update to use .f filename override annotations

* Move top generation to def to help GC
 2019-07-30 22:42:05 -07:00
Albert Magyar
e3c822709b Filter all EmittedAnnotations from JSON emission (#64) 
* Filter all EmittedAnnotations from JSON emission

* Filter more annotations
 2019-07-29 20:39:07 -07:00
John Wright
82636b3ff4 Upstream MemConf and use it (with some slight tweaks) 2019-05-14 10:10:47 -07:00
Colin Schmidt
c23b2b6f84 SRAM depth to bigint 
max synflop depth support
Fix annotation mangling on the harness side
 2019-05-14 10:10:47 -07:00
John Wright
e548210ef4 Add options to emit top/harness firrtl and annotations (#54) 2019-03-29 13:55:18 -07:00
Colin Schmidt
8f7af5b0bf Fix annos (#53) 
* Fixes #36 by using the renamemap
* Also fix harness passes annotation handling h/t azidar
* Remove old comment
 2019-03-27 17:20:41 -07:00
Colin Schmidt
affd033f0a Emit hammer IR from MacroCompiler (#50) 2019-03-25 22:52:39 -07:00
Colin Schmidt
fdad525007 HighForm has whens so we need to check for instances there (#49) 
Fixes a bug
 2019-03-18 11:25:58 -07:00