wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Forgot to update the verilog modules

Browse Source
This commit is contained in:
John Wright
2020-03-30 13:50:27 -07:00
parent 62df79934e
commit bc3f8a42b3
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
iocell/src/main/resources/barstools/iocell/vsrc/IOCell.v
View File

@@ -2,7 +2,7 @@
`timescale 1ns/1ps
module ExampleAnalogIOCell(
module GenericAnalogIOCell(
inout pad,
inout core
);
@@ -12,7 +12,7 @@ module ExampleAnalogIOCell(
endmodule
module ExampleDigitalGPIOCell(
module GenericDigitalGPIOCell(
inout pad,
output i,
input ie,
@@ -25,7 +25,7 @@ module ExampleDigitalGPIOCell(
endmodule
module ExampleDigitalInIOCell(
module GenericDigitalInIOCell(
input pad,
output i,
input ie
@@ -35,7 +35,7 @@ module ExampleDigitalInIOCell(
endmodule
module ExampleDigitalOutIOCell(
module GenericDigitalOutIOCell(
output pad,
input o,
output oe