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Merge pull request #69 from ucb-bar/abejgonzalez-patch-1

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Fix macrocompiler for RW mask port
This commit is contained in:
Abraham Gonzalez
2019-11-04 13:23:05 -08:00
committed by GitHub
parent 26096e07f6 6c59cac744
commit 8b0ef4d770
3 changed files with 112 additions and 1 deletions
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2
macros/src/main/scala/MacroCompiler.scala
View File

@@ -511,7 +511,7 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
/* Palmer: If we don't have a chip enable but do have mask ports. */
stmts += connectPorts(memMask, mask, mask_polarity)
stmts += connectPorts(andAddrMatch(and(memWriteEnable, memChipEnable)),
we, mask_polarity)
we, we_polarity)
case (None, Some(PolarizedPort(we, we_polarity)), chipEnable) =>
if (bitWidth(memMask.tpe) == 1) {
/* Palmer: If we're expected to provide mask ports without a

27
macros/src/test/resources/lib-MaskPortTest.json Normal file
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@@ -0,0 +1,27 @@
[
{
"type" : "sram",
"name" : "fake_mem",
"width" : 64,
"depth" : "512",
"mux" : 4,
"family" : "1rw",
"ports" : [ {
"address port name" : "addr",
"address port polarity" : "active high",
"clock port name" : "clk",
"clock port polarity" : "positive edge",
"write enable port name" : "wen",
"write enable port polarity" : "active high",
"read enable port name" : "ren",
"read enable port polarity" : "active high",
"output port name" : "dataout",
"output port polarity" : "active high",
"input port name" : "datain",
"input port polarity" : "active high",
"mask port name" : "mport",
"mask port polarity" : "active low",
"mask granularity" : 1
} ]
}
]

84
macros/src/test/scala/SpecificExamples.scala
View File

@@ -22,6 +22,90 @@ class GenerateSomeVerilog extends MacroCompilerSpec with HasSRAMGenerator with H
}
}
class MaskPortTest extends MacroCompilerSpec with HasSRAMGenerator {
val mem = s"mem-MaskPortTest.json" // mem. you want to create
val lib = s"lib-MaskPortTest.json" // lib. of mems to create it
val v = s"MaskPortTest.json"
override val libPrefix = "macros/src/test/resources"
val memSRAMs = mdf.macrolib.Utils.readMDFFromString(
"""
[ {
"type" : "sram",
"name" : "cc_dir_ext",
"width" : 128,
"depth" : "512",
"mux" : 1,
"ports" : [ {
"address port name" : "RW0_addr",
"address port polarity" : "active high",
"clock port name" : "RW0_clk",
"clock port polarity" : "positive edge",
"write enable port name" : "RW0_wmode",
"write enable port polarity" : "active high",
"chip enable port name" : "RW0_en",
"chip enable port polarity" : "active high",
"output port name" : "RW0_rdata",
"output port polarity" : "active high",
"input port name" : "RW0_wdata",
"input port polarity" : "active high",
"mask port name" : "RW0_wmask",
"mask port polarity" : "active high",
"mask granularity" : 16
} ],
"family" : "1rw"
} ]
""").getOrElse(List())
writeToMem(mem, memSRAMs)
val output =
"""
circuit cc_dir_ext :
module cc_dir_ext :
input RW0_addr : UInt<9>
input RW0_clk : Clock
input RW0_wdata : UInt<128>
output RW0_rdata : UInt<128>
input RW0_en : UInt<1>
input RW0_wmode : UInt<1>
input RW0_wmask : UInt<8>
inst mem_0_0 of fake_mem
inst mem_0_1 of fake_mem
mem_0_0.clk <= RW0_clk
mem_0_0.addr <= RW0_addr
node RW0_rdata_0_0 = bits(mem_0_0.dataout, 63, 0)
mem_0_0.datain <= bits(RW0_wdata, 63, 0)
mem_0_0.ren <= and(not(RW0_wmode), UInt<1>("h1"))
mem_0_0.mport <= not(cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 3, 3), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 2, 2), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 1, 1), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), cat(bits(RW0_wmask, 0, 0), bits(RW0_wmask, 0, 0)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
mem_0_0.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1"))
mem_0_1.clk <= RW0_clk
mem_0_1.addr <= RW0_addr
node RW0_rdata_0_1 = bits(mem_0_1.dataout, 63, 0)
mem_0_1.datain <= bits(RW0_wdata, 127, 64)
mem_0_1.ren <= and(not(RW0_wmode), UInt<1>("h1"))
mem_0_1.mport <= not(cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 7, 7), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 6, 6), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 5, 5), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), cat(bits(RW0_wmask, 4, 4), bits(RW0_wmask, 4, 4)))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))
mem_0_1.wen <= and(and(RW0_wmode, RW0_en), UInt<1>("h1"))
node RW0_rdata_0 = cat(RW0_rdata_0_1, RW0_rdata_0_0)
RW0_rdata <= mux(UInt<1>("h1"), RW0_rdata_0, UInt<1>("h0"))
extmodule fake_mem :
input addr : UInt<9>
input clk : Clock
input datain : UInt<64>
output dataout : UInt<64>
input ren : UInt<1>
input wen : UInt<1>
input mport : UInt<64>
defname = fake_mem
"""
compileExecuteAndTest(mem, lib, v, output)
}
class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {
val mem = s"mem-BOOMTest.json"
val lib = s"lib-BOOMTest.json"