John Wright
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acd76e5410
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Adding barstools to separate the top from harness and to generate the
memories as external modules, which makes VLSI flows easier to plug in.
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2019-02-13 21:13:08 -08:00 |
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Edward Wang
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d48587b671
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Update project-template for testchipip master
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2018-11-02 12:05:36 -07:00 |
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Albert Ou
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048492e54c
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mk: Ensure that FIRRTL jar has updated timestamp
SBT does not replace $(ROCKETCHIP_DIR)/firrtl/utils/bin/firrtl.jar if
compilation produces the same results.
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2018-10-02 17:43:51 -07:00 |
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Albert Ou
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220aeea4c8
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Bump rocket-chip
- Update Scala version to 2.12.4; work around SBT multi-project idiosyncrasies
- Remove HasSystemErrorSlave
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2018-09-29 13:30:07 -07:00 |
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Howard Mao
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a3684d01dd
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use build.sbt instead of jar files to collect packages
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2018-05-03 17:09:59 -07:00 |
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Howard Mao
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4c8c6e29f0
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update rocket-chip again
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2018-04-18 17:13:07 -07:00 |
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Howard Mao
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7e70e3525f
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move bootrom to testchipip
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2018-04-17 15:13:47 -07:00 |
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Howard Mao
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d88c2fa84f
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add regression tests to makefile
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2018-02-23 13:48:45 -08:00 |
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Howard Mao
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073c16961e
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make sure annotations are generated and carried through to verilog elaboration
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2018-02-23 11:50:33 -08:00 |
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Howard Mao
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1dfe9b1c9f
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bump rocket-chip and fix deprecated code in testchipip.GeneratorApp
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2018-02-23 11:46:40 -08:00 |
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Howard Mao
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e4a4046375
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get RV32 working
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2017-11-03 18:00:27 -07:00 |
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Colin Schmidt
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24cb846812
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Build firrtl first so we dont get that weird error
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2017-07-13 16:58:52 -07:00 |
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Howard Mao
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062d443863
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upgrade to latest rocket-chip
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2017-05-25 12:55:52 -07:00 |
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Howard Mao
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7074420aba
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initial commit
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2016-10-21 16:03:26 -07:00 |
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