Jerry Zhao
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4f5bbdca97
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Flip serial_tl.clock for firechip BridgeBinders
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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9566667767
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Remove bus-to-bus crossings
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2023-05-07 22:22:37 -07:00 |
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Jerry Zhao
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5f076b184d
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Flip serial_tl_clock to be generated off-chip
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2023-05-07 22:22:36 -07:00 |
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Jerry Zhao
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4eb0f81c16
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Bump testchipip
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2023-05-07 16:02:23 -07:00 |
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Jerry Zhao
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954dab1638
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Merge remote-tracking branch 'origin/main' into tcdtm
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2023-05-07 15:56:55 -07:00 |
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Jerry Zhao
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2271194131
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Merge remote-tracking branch 'origin/main' into bump-fs
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2023-05-06 19:26:20 -07:00 |
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Jerry Zhao
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257e7d7507
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Check that HarnessClockInstantiator doesn't receive requests for similarly-named-clocks with different frequencies (#1460)
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2023-05-05 17:09:07 -07:00 |
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Jerry Zhao
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b8ccb7d4f6
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Support not instantiating the TileClockGater/ResetSetter PRCI controllers (#1459)
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2023-05-04 17:15:38 -07:00 |
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Jerry Zhao
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b05f36df79
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Fix support for no-bootROM systems (#1458)
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2023-05-03 18:23:36 -07:00 |
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Jerry Zhao
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1cc5ea5192
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Fix no-uart configs (#1457)
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2023-05-03 18:23:16 -07:00 |
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Jerry Zhao
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a299dae1a5
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Initialize cospike memory from SimDRAM memory
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2023-05-01 09:28:55 -07:00 |
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Tianrui Wei
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64e8f334ac
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fix: address comments
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
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2023-04-20 16:19:16 -07:00 |
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Tianrui Wei
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c5002ab9d3
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fix: address comments
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
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2023-04-20 16:10:40 -07:00 |
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Tianrui Wei
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91ccc7b25d
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feat: cospike changes
Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
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2023-04-20 15:42:08 -07:00 |
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abejgonzalez
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2bf8f258ad
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Bump Gemmini
|
2023-04-20 13:22:19 -07:00 |
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Jerry Zhao
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6701b85f27
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Bump testchipip
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2023-04-19 23:48:14 -07:00 |
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Jerry Zhao
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104a5299a9
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Fix typos
|
2023-04-19 19:52:46 -07:00 |
|
Jerry Zhao
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383a0fee96
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Bump testchipip to standardize tlserdes bundle params
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2023-04-19 11:44:20 -07:00 |
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Jerry Zhao
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2b3c5fc48e
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Merge remote-tracking branch 'origin/main' into tcdtm
|
2023-04-17 18:14:43 -07:00 |
|
Jerry Zhao
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4038217ae9
|
Serial-TL backing memory configs should use 1 memory channel
|
2023-04-17 17:56:44 -07:00 |
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Jerry Zhao
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c6bf50bc9d
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Update verilator's emulator.cc SIM_FILE_REQS
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2023-04-17 16:20:52 -07:00 |
|
Jerry Zhao
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ad9ea333d1
|
Bump TestChipIp to improve default serial_tl behavior
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2023-04-17 14:14:24 -07:00 |
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Jerry Zhao
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8c47f50a73
|
Restore vector state as well for cosim loadarch
|
2023-04-17 14:07:37 -07:00 |
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Jerry Zhao
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a7a441b6a8
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Bump testchipip
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2023-04-17 13:25:19 -07:00 |
|
Jerry Zhao
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07e19e5bb8
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Increase debug module data capacity
|
2023-04-17 11:56:12 -07:00 |
|
Jerry Zhao
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048835e6b4
|
Add dmi/cosim boomconfigs
|
2023-04-13 17:49:57 -07:00 |
|
Jerry Zhao
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330a747b54
|
Support loadarch+dtm in cosimulation with spike
|
2023-04-13 17:49:39 -07:00 |
|
Jerry Zhao
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d2422ec229
|
Fix debug priv trace for boom
|
2023-04-13 17:01:19 -07:00 |
|
Jerry Zhao
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a30b5c4c51
|
Use __has_include to select between dtm/tsi spiketile
|
2023-04-13 15:15:46 -07:00 |
|
Jerry Zhao
|
a31685af40
|
Bump testchipip
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2023-04-12 17:55:07 -07:00 |
|
Jerry Zhao
|
1acad86161
|
Generate loadarch checkpoints in directories
|
2023-04-12 17:27:07 -07:00 |
|
joey0320
|
b41806b6a0
|
bump testchipip
|
2023-04-12 17:25:17 -07:00 |
|
Jerry Zhao
|
02a10f358b
|
Add dmiUltraFastSpikeConfig
|
2023-04-12 17:24:15 -07:00 |
|
Jerry Zhao
|
3771e62a20
|
Default to 2 memory channels in AbstractConfig
|
2023-04-12 17:24:15 -07:00 |
|
Jerry Zhao
|
f5ceab2077
|
Pass base of memory to SimDRAM
|
2023-04-12 17:24:15 -07:00 |
|
Jerry Zhao
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e51b3e8c61
|
Fix SpikeTile TCM with loadmem-by-elf
|
2023-04-12 17:24:15 -07:00 |
|
Jerry Zhao
|
6a97f2eb97
|
Support dmi-based Spike bringup
|
2023-04-12 17:23:59 -07:00 |
|
Jerry Zhao
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4adb8d91c1
|
Fix ChipLikeQuadRocketConfig crossing
There needs to be a crossing between sbus/fbus when they are on separate clock domains
|
2023-04-11 17:44:24 -07:00 |
|
joey0320
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b36909d2f4
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re-bump
|
2023-04-10 09:37:31 -07:00 |
|
joey0320
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1f5e75c755
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re-bump
|
2023-04-09 20:14:55 -07:00 |
|
joey0320
|
4b620f117c
|
bump testchipip
|
2023-04-09 19:36:56 -07:00 |
|
Jerry Zhao
|
0ffc3c7770
|
Add some comments on harness/chiptop clocking APIs
|
2023-04-08 17:19:25 -07:00 |
|
Jerry Zhao
|
de293f5fdf
|
Add build of ChipLikeQuadRocketConfig to CI
|
2023-04-08 15:58:18 -07:00 |
|
Jerry Zhao
|
b88e1025e4
|
Add comments on ResetStretchers
|
2023-04-08 15:24:28 -07:00 |
|
Jerry Zhao
|
b7b2a62d80
|
Update clocking stuff to chisel 3.5.6
|
2023-04-08 15:24:28 -07:00 |
|
Jerry Zhao
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32f0f83900
|
[ci skip] Update comments for FakePLLClockBinder
|
2023-04-08 15:24:28 -07:00 |
|
Jerry Zhao
|
70643335d2
|
Fix RationalRockettiles not getting picked up in MulticlockRocketConfig
|
2023-04-08 15:24:28 -07:00 |
|
Jerry Zhao
|
f1b17b533b
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Add examples of ChipLikeRocketConfig/FlatChipTop/FlatTestHarness
|
2023-04-08 15:24:28 -07:00 |
|
Jerry Zhao
|
70ea3b78ab
|
Add ChipLikeRocketConfig ... improve harness clocking APIs
|
2023-04-08 15:24:28 -07:00 |
|
Jerry Zhao
|
8a1ebb090c
|
Move Clock binders to separate file
|
2023-04-08 15:24:28 -07:00 |
|