Add examples of ChipLikeRocketConfig/FlatChipTop/FlatTestHarness
This commit is contained in:
Jerry Zhao
@@ -103,9 +103,14 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
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// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
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// with a blackbox of whatever PLL is being integrated
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val fakeClockSource = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
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fakeClockSource.io.power := pllCtrlSink.in(0)._1.power
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fakeClockSource.io.gate := pllCtrlSink.in(0)._1.gate
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val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
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fake_pll.io.power := pllCtrlSink.in(0)._1.power
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fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
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pllClockSource.out.unzip._1.map { o =>
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o.clock := fake_pll.io.clk
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o.reset := reset_wire
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}
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(Seq(clock_io, reset_io), clockIOCell ++ resetIOCell)
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}
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44
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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44
generators/chipyard/src/main/scala/config/ChipConfigs.scala
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package chipyard
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import freechips.rocketchip.config.{Config}
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import freechips.rocketchip.diplomacy._
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// A simple config demonstrating how to set up a basic chip in Chipyard
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class ChipLikeRocketConfig extends Config(
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//==================================
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// Set up TestHarness
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//==================================
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new chipyard.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
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// NOTE: This only simulates properly in VCS
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//==================================
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// Set up tiles
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//==================================
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new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add rational crossings between RocketTile and uncore
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new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles)
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//==================================
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// Set up I/O
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//==================================
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new testchipip.WithSerialTLWidth(4) ++
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new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness
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new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory
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//==================================
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// Set up clock./reset
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//==================================
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new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++ // Use a PLL-based clock selector/divider generator structure
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// Create two clock groups, uncore and fbus, in addition to the tile clock groups
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new chipyard.clocking.WithClockGroupsCombinedByName("uncore", "implicit", "sbus", "mbus", "cbus", "system_bus") ++
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new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++
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// Set up the crossings
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new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
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new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
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new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
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new testchipip.WithSerialTLAsyncResetQueue ++ // Add Async reset queue to block ready while in reset
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new chipyard.config.AbstractConfig)
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143
generators/chipyard/src/main/scala/example/FlatChipTop.scala
Normal file
143
generators/chipyard/src/main/scala/example/FlatChipTop.scala
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@@ -0,0 +1,143 @@
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package chipyard.example
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import chisel3._
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.prci._
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import freechips.rocketchip.util._
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import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
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import freechips.rocketchip.tilelink.{TLBuffer}
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import chipyard.{BuildSystem, DigitalTop}
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import chipyard.clocking._
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import chipyard.iobinders.{IOCellKey, JTAGChipIO}
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import barstools.iocell.chisel._
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// This "FlatChipTop" uses no IOBinders, so all the IO have
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// to be explicitly constructed.
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// This only supports the base "DigitalTop"
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class FlatChipTop(implicit p: Parameters) extends LazyModule {
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override lazy val desiredName = "ChipTop"
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val system = LazyModule(p(BuildSystem)(p)).suggestName("system").asInstanceOf[DigitalTop]
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//========================
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// Diplomatic clock stuff
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//========================
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val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
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system.connectImplicitClockSinkNode(implicitClockSinkNode)
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val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere)
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val baseAddress = system.prciParams.baseAddress
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val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
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val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
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val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
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tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
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tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
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tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
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system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
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// Connect all other requested clocks
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val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
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val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
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// The order of the connections to clockSelector.clockNode configures what
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clockSelector.clockNode := slowClockSource
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clockSelector.clockNode := pllClockSource
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val pllCtrlSink = BundleBridgeSink[FakePLLCtrlBundle]()
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pllCtrlSink := pllCtrl.ctrlNode
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val debugClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters()))
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debugClockSinkNode := system.locateTLBusWrapper(p(ExportDebug).slaveWhere).fixedClockNode
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def debugClockBundle = debugClockSinkNode.in.head._1
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override lazy val module = new FlatChipTopImpl
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class FlatChipTopImpl extends LazyRawModuleImp(this) {
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//=========================
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// Clock/reset
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//=========================
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val implicit_clock = implicitClockSinkNode.in.head._1.clock
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val implicit_reset = implicitClockSinkNode.in.head._1.reset
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system.module match { case l: LazyModuleImp => {
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l.clock := implicit_clock
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l.reset := implicit_reset
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}}
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val clock_wire = Wire(Input(new ClockWithFreq(80)))
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val reset_wire = Wire(Input(AsyncReset()))
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val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
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val (reset_pad, resetIOCell) = IOCell.generateIOFromSignal(reset_wire, "reset", p(IOCellKey))
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slowClockSource.out.unzip._1.map { o =>
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o.clock := clock_wire.clock
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o.reset := reset_wire
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}
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// For a real chip you should replace this ClockSourceAtFreqFromPlusArg
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// with a blackbox of whatever PLL is being integrated
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val fake_pll = Module(new ClockSourceAtFreqFromPlusArg("pll_freq_mhz"))
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fake_pll.io.power := pllCtrlSink.in(0)._1.power
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fake_pll.io.gate := pllCtrlSink.in(0)._1.gate
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pllClockSource.out.unzip._1.map { o =>
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o.clock := fake_pll.io.clk
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o.reset := reset_wire
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}
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//=========================
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// Custom Boot
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//=========================
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val (custom_boot_pad, customBootIOCell) = IOCell.generateIOFromSignal(system.custom_boot_pin.get.getWrappedValue, "custom_boot", p(IOCellKey))
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//=========================
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// Serialized TileLink
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//=========================
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val (serial_tl_pad, serialTLIOCells) = IOCell.generateIOFromSignal(system.serial_tl.get.getWrappedValue, "serial_tl", p(IOCellKey))
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//=========================
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// JTAG/Debug
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//=========================
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val debug = system.module.debug.get
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// We never use the PSDIO, so tie it off on-chip
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system.module.psd.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode) }
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system.module.resetctrl.map { rcio => rcio.hartIsInReset.map { _ := false.B } }
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// Tie off extTrigger
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debug.extTrigger.foreach { t =>
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t.in.req := false.B
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t.out.ack := t.out.req
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}
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// Tie off disableDebug
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debug.disableDebug.foreach { d => d := false.B }
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// Drive JTAG on-chip IOs
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debug.systemjtag.map { j =>
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j.reset := ResetCatchAndSync(j.jtag.TCK, debugClockBundle.reset.asBool)
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j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
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j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
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j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
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}
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Debug.connectDebugClockAndReset(Some(debug), debugClockBundle.clock)
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// Add IOCells for the DMI/JTAG/APB ports
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require(!debug.clockeddmi.isDefined)
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require(!debug.apb.isDefined)
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val (jtag_pad, jtagIOCells) = debug.systemjtag.map { j =>
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val jtag_wire = Wire(new JTAGChipIO)
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j.jtag.TCK := jtag_wire.TCK
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j.jtag.TMS := jtag_wire.TMS
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j.jtag.TDI := jtag_wire.TDI
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jtag_wire.TDO := j.jtag.TDO.data
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IOCell.generateIOFromSignal(jtag_wire, "jtag", p(IOCellKey), abstractResetAsAsync = true)
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}.get
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//==========================
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// UART
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//==========================
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require(system.uarts.size == 1)
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val (uart_pad, uartIOCells) = IOCell.generateIOFromSignal(system.module.uart.head, "uart_0", p(IOCellKey))
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}
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}
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@@ -0,0 +1,83 @@
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package chipyard.example
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import chisel3._
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import scala.collection.mutable.{ArrayBuffer, LinkedHashMap}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.prci.{ClockSourceAtFreqFromPlusArg, ClockBundle, ClockBundleParameters}
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import freechips.rocketchip.util.{PlusArg}
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import freechips.rocketchip.subsystem.{CacheBlockBytes}
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import freechips.rocketchip.devices.debug.{SimJTAG}
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import freechips.rocketchip.jtag.{JTAGIO}
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import testchipip.{SerialTLKey, SerialAdapter, UARTAdapter, SimDRAM}
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import chipyard.{BuildTop}
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// A "flat" TestHarness that doesn't use IOBinders
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// use with caution.
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// This example is hard-coded to work only for FlatChipTop, and the ChipLikeRocketConfig
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class FlatTestHarness(implicit val p: Parameters) extends Module {
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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// This only works with FlatChipTop
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val lazyDut = LazyModule(new FlatChipTop).suggestName("chiptop")
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val dut = Module(lazyDut.module)
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// Clock
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val clock_source = Module(new ClockSourceAtFreqFromPlusArg("slow_clk_freq_mhz"))
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clock_source.io.power := true.B
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clock_source.io.gate := false.B
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dut.clock_pad.clock := clock_source.io.clk
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// Reset
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dut.reset_pad := reset.asAsyncReset
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// Custom boot
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dut.custom_boot_pad := PlusArg("custom_boot_pin", width=1)
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// Serialized TL
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val sVal = p(SerialTLKey).get
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require(sVal.axiMemOverSerialTLParams.isDefined)
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require(sVal.isMemoryDevice)
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val axiDomainParams = sVal.axiMemOverSerialTLParams.get
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val memFreq = axiDomainParams.getMemFrequency(lazyDut.system)
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withClockAndReset(clock, reset) {
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val memOverSerialTLClockBundle = Wire(new ClockBundle(ClockBundleParameters()))
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memOverSerialTLClockBundle.clock := clock
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memOverSerialTLClockBundle.reset := reset
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val serial_bits = SerialAdapter.asyncQueue(dut.serial_tl_pad, clock, reset)
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val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
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lazyDut.system.serdesser.get,
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serial_bits,
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memOverSerialTLClockBundle,
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reset)
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io.success := SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, clock, reset)
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// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
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(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
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val memSize = sVal.memParams.size
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val lineSize = p(CacheBlockBytes)
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val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram")
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mem.io.axi <> axi_port.bits
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mem.io.clock := axi_port.clock
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mem.io.reset := axi_port.reset
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}
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}
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// JTAG
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val jtag_wire = Wire(new JTAGIO)
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jtag_wire.TDO.data := dut.jtag_pad.TDO
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jtag_wire.TDO.driven := true.B
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dut.jtag_pad.TCK := jtag_wire.TCK
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dut.jtag_pad.TMS := jtag_wire.TMS
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dut.jtag_pad.TDI := jtag_wire.TDI
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val dtm_success = WireInit(false.B)
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val jtag = Module(new SimJTAG(tickDelay=3)).connect(jtag_wire, clock, reset.asBool, ~(reset.asBool), dtm_success)
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// UART
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UARTAdapter.connect(Seq(dut.uart_pad))
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}
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