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  • 9706a4e09d minor update Blaise Tine 2020-06-20 18:13:15 -04:00
  • d3440de403 round robin arbiter + auto buffered queue + fixed dcache arbiter Blaise Tine 2020-06-20 17:56:04 -04:00
  • 9c157e4929 minor update Blaise Tine 2020-06-19 14:50:02 -04:00
  • de0ff93fe5 minor cleanup Blaise Tine 2020-06-19 09:25:24 -07:00
  • 68d9fc9a75 driver basic test and demo test refactoring Blaise Tine 2020-06-19 09:12:07 -07:00
  • e2e1b63e14 refactor synthesis scripts + fixed quartus ram read-after-write bypass Blaise Tine 2020-06-16 11:45:47 -07:00
  • 9850a1f890 minor fixes Blaise Tine 2020-06-15 00:20:56 -07:00
  • 75af29febb scope refactoring Blaise Tine 2020-06-13 11:47:28 -07:00
  • 4fa540575c fixed gpr_ram bug + io bus arbitration Blaise Tine 2020-06-13 05:26:29 -07:00
  • d6b0ef2b3c scope refactoring + snoop invalidate Blaise Tine 2020-06-12 00:04:31 -07:00
  • 19f263c772 scope fixes Blaise Tine 2020-06-09 20:49:36 -07:00
  • 1688c65050 scope fixes Blaise Tine 2020-06-09 10:19:28 -04:00
  • 457783322b scope fixes Blaise Tine 2020-06-09 07:03:52 -07:00
  • 9575fe9a51 scope fixes Blaise Tine 2020-06-08 06:54:47 -07:00
  • 170c88f295 scope fixes Blaise Tine 2020-06-08 04:25:28 -07:00
  • abc09eb1a3 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-06-05 22:59:26 -07:00
  • 765462ceea minor update Blaise Tine 2020-06-05 22:59:07 -07:00
  • 9ae38433fb VX_pipeline refactoring + logic analyzer Blaise Tine 2020-06-06 01:52:44 -04:00
  • 203ebb3445 minor update Blaise Tine 2020-06-04 15:53:04 -07:00
  • c4f2488dbe Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-06-04 15:44:40 -07:00
  • 4e0e710182 OPAE rtl fixes Blaise Tine 2020-06-04 15:44:03 -07:00
  • 171d46b501 fix l2 cache issues Blaise Tine 2020-06-04 18:34:14 -04:00
  • ea890b457d fixed msrq regression Blaise Tine 2020-06-03 17:22:24 -04:00
  • 9eb0389717 minor update Blaise Tine 2020-06-03 06:40:25 -04:00
  • 626a4f6fc1 merge Blaise Tine 2020-06-03 06:25:34 -04:00
  • 106d707024 verilator suppor for opae (partial) Blaise Tine 2020-06-03 06:22:49 -04:00
  • 04fc34b848 minor update Blaise Tine 2020-06-03 03:05:45 -07:00
  • 9b186dcc6e fixed L2 cache Blaise Tine 2020-06-02 05:32:50 -07:00
  • e01c411b20 opae rtl fixes Blaise Tine 2020-06-01 23:06:13 -07:00
  • 16d5a8a09c opae rtl fixes Blaise Tine 2020-05-31 14:51:42 -07:00
  • 6a3b237054 minor update Blaise Tine 2020-05-29 00:57:59 -04:00
  • 033381ab6f Force correct word selection when BANK_LINE_WORD=1 felsabbagh3 2020-05-28 20:39:39 -07:00
  • 33b273b204 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-28 18:34:25 -04:00
  • b930a822ad minor updates Blaise Tine 2020-05-28 18:34:03 -04:00
  • 611ceb000a fixed warp_sched lock bug Blaise Tine 2020-05-28 08:52:20 -04:00
  • 98b98b1005 remove riscv_test bin files Blaise Tine 2020-05-27 19:01:36 -04:00
  • 9e5885b820 adding dram writeenable support + scheduler bug fixes Blaise Tine 2020-05-27 19:00:23 -04:00
  • b43dd76d0d fixed typo Tine, Blaise 2020-05-26 23:15:32 -04:00
  • 61231cd2af OPAE rtl fixes Blaise Tine 2020-05-24 02:42:56 -07:00
  • a9f896b4f3 fixed snoop forwarding bug and single bank support Blaise Tine 2020-05-24 04:29:43 -04:00
  • 47ed6b18ff Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-24 01:37:55 -04:00
  • a1e9b512b0 Added mrvq_recover_ready_state_st2 to optimize fills sent felsabbagh3 2020-05-23 21:47:51 -07:00
  • 0cd9bd689e Added schedule_ptr to mrvq for speculative pops felsabbagh3 2020-05-23 21:36:57 -07:00
  • 3a9e79d979 revert byte_enable tag structure Blaise Tine 2020-05-23 22:23:25 -04:00
  • c54fa50715 fixed snoop forwarder dequue to support out of order responses Blaise Tine 2020-05-23 20:19:54 -04:00
  • 9398c07afb optimized avs_pending_reads in vortex_afu.sv Blaise Tine 2020-05-23 19:54:37 -04:00
  • 507622f1a1 fixed simulator snoop handling Blaise Tine 2020-05-23 19:26:59 -04:00
  • 6882d88a62 removed fill_invalidator (not needed anymore) Blaise Tine 2020-05-23 19:24:52 -04:00
  • f3b21aab8f remove unsued cache parameter LLVQ_SIZE Blaise Tine 2020-05-23 00:33:51 -04:00
  • 70dadca9fe fix scheduler rename_table X values - reverted valid bits Blaise Tine 2020-05-23 00:22:56 -04:00
  • 1512138a15 minor update Blaise Tine 2020-05-22 19:14:07 -07:00
  • b02fc14da6 fill invalifator fix + refactoring Blaise Tine 2020-05-21 20:38:55 -07:00
  • 70c70407c9 minor update Blaise Tine 2020-05-21 12:08:16 -07:00
  • 002a28e568 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-21 14:52:36 -04:00
  • 3c8620e770 minor update Blaise Tine 2020-05-21 14:51:56 -04:00
  • cf22ef2bf3 minor update Blaise Tine 2020-05-21 13:42:08 -04:00
  • 8daab1c22b Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-21 01:11:38 -07:00
  • d12c40131e optimize generic_queue to support simple model for smaller size queues Blaise Tine 2020-05-21 04:04:27 -04:00
  • 276fa5c919 optimize generic_queue to support simple model for smaller size queues Blaise Tine 2020-05-21 03:34:03 -04:00
  • 3f5fa64085 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-21 00:00:29 -07:00
  • f14996b4ae minor update Blaise Tine 2020-05-20 23:54:27 -07:00
  • 7e091b53f8 Added valid_table in scheduler and removed rename_table on reset felsabbagh3 2020-05-20 23:02:41 -07:00
  • a8bf62a168 minor update Blaise Tine 2020-05-20 21:05:29 -04:00
  • 240bdae13d minor update Blaise Tine 2020-05-20 20:58:17 -04:00
  • 1102871180 force random values for unitialized signals Blaise Tine 2020-05-20 20:57:15 -04:00
  • 7e5fed3ec1 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-20 18:27:20 -04:00
  • d4cb8b6f66 fixed renaem table reset logic Blaise Tine 2020-05-20 18:24:09 -04:00
  • 72d54c749c fixed cache msrq reset logic Blaise Tine 2020-05-20 18:11:31 -04:00
  • e1b4862f85 minor update Blaise Tine 2020-05-20 14:14:29 -07:00
  • cefd0d85af rtl refactoring Blaise Tine 2020-05-20 16:59:14 -04:00
  • b5569dd525 OPAE rtl fixes Blaise Tine 2020-05-20 12:08:10 -07:00
  • e3bead147a erge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-05-19 17:40:45 -07:00
  • c37e6e2207 opae rtl fixes Blaise Tine 2020-05-19 17:36:18 -07:00
  • cad92bbeb1 Qualify scheduler_delay with valid signal felsabbagh3 2020-05-19 14:59:17 -07:00
  • c209d902a3 update Blaise Tine 2020-05-19 17:41:51 -04:00
  • e269909db9 opae rtl fixes Blaise Tine 2020-05-19 13:47:47 -07:00
  • 0c88da2bfb opae rtl fixes Blaise Tine 2020-05-18 20:19:02 -07:00
  • 11ace25f27 opae rtl fixes Blaise Tine 2020-05-17 20:29:42 -07:00
  • 26f9fc96c3 Corner case where the pipeline is stalled, makes mrvq entereis valid, but when unstalled mrvq_init isn't set up correctly felsabbagh3 2020-05-16 21:20:57 -07:00
  • 101de6b138 mrvq update ready + init ready as 1 in same cycle causing incorrect ready state felsabbagh3 2020-05-16 18:52:30 -07:00
  • 794664363c Commented rtlsim dynamiclib for mac felsabbagh3 2020-05-16 18:02:37 -07:00
  • f55a1be6cb Commented mac dynamiclib in basic felsabbagh3 2020-05-16 18:01:20 -07:00
  • 4bf0bcca8a Fix incorrect CSR forwarding for GID between different warps felsabbagh3 2020-05-16 17:56:15 -07:00
  • e2741f9cdb Force miss_add init ready to 1 when core req matches with mrvq entry, regardless of hit/miss felsabbagh3 2020-05-16 16:26:26 -07:00
  • 544f272ff9 update Blaise Tine 2020-05-16 18:16:14 -04:00
  • d6c87dbb0a added debug print states or rtl Blaise Tine 2020-05-16 14:19:17 -04:00
  • 65c2da76cf snooping response handling fix Blaise Tine 2020-05-14 23:34:52 -04:00
  • 57a037b2f4 snooping response handling fix Blaise Tine 2020-05-14 23:06:15 -04:00
  • d623ef4029 snooping response handling fix Blaise Tine 2020-05-14 23:05:46 -04:00
  • bcb9514799 snooping response handling fix Blaise Tine 2020-05-14 11:01:41 -04:00
  • ff140b6811 Added an initial ready state to an mrvq entry that might be set to 1 felsabbagh3 2020-05-12 21:47:51 -07:00
  • 5b2624046e Avoid snoop deadlock whith snoops. Adds mrvq not almost full for snrq pop felsabbagh3 2020-05-12 21:30:17 -07:00
  • b08b80156d Added pending request check. This applies when 1) mrvq entery is valid/ready but not head, then a core request hits 2) snoop when pending write. A pending miss request is either a valid entry in mrvq OR a miss entery in st2 felsabbagh3 2020-05-12 21:25:13 -07:00
  • b0b38f6c24 snooping response handling fix Blaise Tine 2020-05-12 18:52:24 -04:00
  • 1eda9b34d5 snooping response handling fix Blaise Tine 2020-05-12 13:36:55 -04:00
  • fcf3800d5d snooping response handling fix Blaise Tine 2020-05-12 13:35:18 -04:00
  • c49f01b769 snooping response handling Blaise Tine 2020-05-11 22:55:44 -04:00
  • b6c4aa0baa rtl refactoring Blaise Tine 2020-05-10 09:52:38 -04:00
  • cc84e0691c multicore fix Blaise Tine 2020-05-10 08:30:04 -04:00
  • 359601cfd3 OPAE rtl fixes Blaise Tine 2020-05-08 13:16:44 -07:00