force random values for unitialized signals

driver/rtlsim/Makefile

@@ -34,6 +34,8 @@ VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(MULTICORE)
 CFLAGS += -DGLOBAL_BLOCK_SIZE=64
 VL_FLAGS += -DGLOBAL_BLOCK_SIZE=64
 
+VL_FLAGS += --x-initial unique
+
 # Enable Verilator multithreaded simulation
 #THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))')
 #VL_FLAGS += --threads $(THREADS)

hw/rtl/VX_scheduler.v

@@ -48,9 +48,15 @@ module VX_scheduler (
                           || (gpr_stage_delay && (is_mem || is_exec))  
                           || (exec_delay && is_exec));
 
+    integer i, w;
+    
     always @(posedge clk) begin
         if (reset) begin
-            //--
+            for (w = 0; w < `NUM_WARPS; w=w+1) begin
+                for (i = 0; i < 32; i++) begin
+                     rename_table[w][i] <= 0;
+                end
+            end
         end else begin
             if (valid_wb) begin
                 rename_table[writeback_if.warp_num][writeback_if.rd] <= rename_table[writeback_if.warp_num][writeback_if.rd] & (~writeback_if.valid);

hw/simulate/simulator.cpp

@@ -9,6 +9,14 @@ double sc_time_stamp() {
 }
 
 Simulator::Simulator() {    
+  // force random values for unitialized signals
+  const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+0"};
+  Verilated::commandArgs(3, args);
+
+#ifndef NDEBUG
+  Verilated::debug(1);
+#endif
+
   ram_ = nullptr;
   vortex_ = new VVortex_Socket();