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opae rtl fixes

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This commit is contained in:
Blaise Tine
2020-05-19 13:47:47 -07:00
parent 0c88da2bfb
commit e269909db9
10 changed files with 46 additions and 53 deletions
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4
driver/tests/basic/basic.cpp
View File

@@ -175,11 +175,11 @@ int main(int argc, char *argv[]) {
RT_CHECK(vx_alloc_shared_mem(device, 4096, &dbuf));
// run tests
if (0 == test || -1 == test) {
/*if (0 == test || -1 == test) {
std::cout << "run memcopy test" << std::endl;
RT_CHECK(run_memcopy_test(sbuf, dbuf, DEV_MEM_SRC_ADDR, 0x0badf00d00ff00ff, 1));
RT_CHECK(run_memcopy_test(sbuf, dbuf, DEV_MEM_SRC_ADDR, 0x0badf00d40ff40ff, 64));
}
}*/
if (1 == test || -1 == test) {
std::cout << "run kernel test" << std::endl;

9
hw/opae/sources.txt
View File

@@ -1,9 +1,14 @@
vortex_afu.json
+define+GLOBAL_BLOCK_SIZE=64
#+define+NUM_CORES=2
#+define+DL2_ENABLE=0
#+define+L2_ENABLE=0
+define+DBG_PRINT_CORE_ICACHE
+define+DBG_PRINT_CORE_DCACHE
+define+DBG_PRINT_BANK
+define+DBG_PRINT_DRAM
+define+DBG_PRINT_SNP_FWD
+incdir+.
+incdir+../rtl

12
hw/opae/vortex_afu.sv
View File

@@ -363,7 +363,7 @@ begin
avs_address <= csr_mem_addr + avs_read_ctr;
avs_read_ctr <= avs_read_ctr + 1;
avs_read <= 1;
$display("%t: AVS Rd Req: addr=%h, pending=%d", $time, (csr_mem_addr + avs_read_ctr), avs_pending_reads);
$display("%t: AVS Rd Req: addr=%h, pending=%0d", $time, (csr_mem_addr + avs_read_ctr), avs_pending_reads);
end
if (cci_dram_req_write_fire) begin
@@ -377,7 +377,7 @@ begin
if (vx_dram_req_read_fire) begin
avs_address <= vx_dram_req_addr;
avs_read <= 1;
$display("%t: AVS Rd Req: addr=%h, pending=%d", $time, vx_dram_req_addr, avs_pending_reads);
$display("%t: AVS Rd Req: addr=%h, pending=%0d", $time, vx_dram_req_addr, avs_pending_reads);
end
if (vx_dram_req_write_fire) begin
@@ -388,7 +388,7 @@ begin
end
if (avs_readdatavalid) begin
$display("%t: AVS Rd Rsp: pending=%d", $time, avs_pending_rds_next);
$display("%t: AVS Rd Rsp: pending=%0d", $time, avs_pending_rds_next);
end
avs_pending_reads <= avs_pending_rds_next;
@@ -513,7 +513,7 @@ begin
if (t_cci_rdq_tag'(cci_read_ctr) == (CCI_RD_WINDOW_SIZE-1)) begin
cci_read_wait <= 1; // end current request batch
end
$display("%t: CCI Rd Req: addr=%h, ctr=%d", $time, cci_read_hdr.address, cci_read_ctr);
$display("%t: CCI Rd Req: addr=%h, ctr=%0d", $time, cci_read_hdr.address, cci_read_ctr);
end
if (cci_rdq_push) begin
@@ -521,7 +521,7 @@ begin
if (cci_rdq_ctr == (CCI_RD_WINDOW_SIZE-1)) begin
cci_read_wait <= 0; // restart new request batch
end
$display("%t: CCI Rd Rsp: idx=%d, ctr=%d", $time, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata), cci_rdq_ctr);
$display("%t: CCI Rd Rsp: idx=%0d, ctr=%0d", $time, t_cci_rdq_tag'(cp2af_sRxPort.c0.hdr.mdata), cci_rdq_ctr);
end
end
end
@@ -595,7 +595,7 @@ begin
end
if (cp2af_sRxPort.c1.rspValid) begin
$display("%t: CCI Wr Rsp: pending=%d", $time, cci_pending_writes_next);
$display("%t: CCI Wr Rsp: pending=%0d", $time, cci_pending_writes_next);
end
cci_pending_writes <= cci_pending_writes_next;

6
hw/rtl/VX_decode.v
View File

@@ -311,12 +311,6 @@ module VX_decode(
assign frE_to_bckE_req_if.alu_op = ((func7[0] == 1'b1) && is_rtype) ? mul_alu : temp_final_alu;
/*always_comb begin
if (1'($time & 1) && (| fd_inst_meta_de.valid)) begin
$display("*** %t: decode: opcode=%h", $time, curr_opcode);
end
end*/
endmodule

10
hw/rtl/VX_icache_stage.v
View File

@@ -63,12 +63,12 @@ module VX_icache_stage #(
end
`ifdef DBG_PRINT_CORE_ICACHE
always_comb begin
if (1'($time & 1) && icache_req_if.core_req_ready && icache_req_if.core_req_valid) begin
$display("*** %t: I%01d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, icache_req_if.core_req_tag, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
always_ff @(posedge clk) begin
if (icache_req_if.core_req_ready && icache_req_if.core_req_valid) begin
$display("%t: I%01d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, icache_req_if.core_req_tag, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num);
end
if (1'($time & 1) && icache_rsp_if.core_rsp_ready && icache_rsp_if.core_rsp_valid) begin
$display("*** %t: I%01d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, icache_rsp_if.core_rsp_tag, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction);
if (icache_rsp_if.core_rsp_ready && icache_rsp_if.core_rsp_valid) begin
$display("%t: I%01d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, icache_rsp_if.core_rsp_tag, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction);
end
end
`endif

10
hw/rtl/VX_lsu_unit.v
View File

@@ -63,12 +63,12 @@ module VX_lsu_unit #(
assign {mem_wb_if.pc, mem_wb_if.wb, mem_wb_if.rd, mem_wb_if.warp_num} = dcache_rsp_if.core_rsp_tag;
`ifdef DBG_PRINT_CORE_DCACHE
always_comb begin
if (1'($time & 1) && dcache_req_if.core_req_ready && (| dcache_req_if.core_req_valid)) begin
$display("*** %t: D%01d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, use_valid, use_address, dcache_req_if.core_req_tag, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, use_store_data);
always_ff @(posedge clk) begin
if (dcache_req_if.core_req_ready && (| dcache_req_if.core_req_valid)) begin
$display("%t: D%01d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, use_valid, use_address, dcache_req_if.core_req_tag, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, use_store_data);
end
if (1'($time & 1) && dcache_rsp_if.core_rsp_ready && (| dcache_rsp_if.core_rsp_valid)) begin
$display("*** %t: D%01d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, dcache_rsp_if.core_rsp_tag, mem_wb_if.pc, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data);
if (dcache_rsp_if.core_rsp_ready && (| dcache_rsp_if.core_rsp_valid)) begin
$display("%t: D%01d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, dcache_rsp_if.core_rsp_tag, mem_wb_if.pc, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data);
end
end
`endif

10
hw/rtl/Vortex_Socket.v
View File

@@ -329,12 +329,12 @@ module Vortex_Socket (
end
`ifdef DBG_PRINT_DRAM
always_comb begin
if (1'($time & 1) && (dram_req_read || dram_req_write) && dram_req_ready) begin
$display("*** %t: DRAM req: w=%b addr=%0h, tag=%0h, data=%0h", $time, dram_req_write, {dram_req_addr, `CLOG2(`GLOBAL_BLOCK_SIZE)'(0)}, dram_req_tag, dram_req_data);
always_ff @(posedge clk) begin
if ((dram_req_read || dram_req_write) && dram_req_ready) begin
$display("%t: DRAM req: w=%b addr=%0h, tag=%0h, data=%0h", $time, dram_req_write, {dram_req_addr, `CLOG2(`GLOBAL_BLOCK_SIZE)'(0)}, dram_req_tag, dram_req_data);
end
if (1'($time & 1) && dram_rsp_valid && dram_rsp_ready) begin
$display("*** %t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data);
if (dram_rsp_valid && dram_rsp_ready) begin
$display("%t: DRAM rsp: tag=%0h, data=%0h", $time, dram_rsp_tag, dram_rsp_data);
end
end
`endif

14
hw/rtl/cache/VX_bank.v vendored
View File

@@ -682,15 +682,15 @@ module VX_bank #(
|| dram_fill_req_stall;
`ifdef DBG_PRINT_BANK
always_comb begin
if (1'($time & 1) && dram_fill_req_valid && dram_fill_req_ready) begin
$display("*** %t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
always_ff @(posedge clk) begin
if (dram_fill_req_valid && dram_fill_req_ready) begin
$display("%t: bank%02d:%01d dram_fill req: addr=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_req_addr, BANK_ID));
end
if (1'($time & 1) && dram_wb_req_valid && dram_wb_req_ready) begin
$display("*** %t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
if (dram_wb_req_valid && dram_wb_req_ready) begin
$display("%t: bank%02d:%01d dram_wb req: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_wb_req_addr, BANK_ID), dram_wb_req_data);
end
if (1'($time & 1) && dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("*** %t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
if (dram_fill_rsp_valid && dram_fill_rsp_ready) begin
$display("%t: bank%02d:%01d dram_fill rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_fill_rsp_addr, BANK_ID), dram_fill_rsp_data);
end
end
`endif

6
hw/rtl/cache/VX_cache.v vendored
View File

@@ -447,11 +447,5 @@ module VX_cache #(
.snp_rsp_tag (snp_rsp_tag),
.snp_rsp_ready (snp_rsp_ready)
);
/*always_comb begin
if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin
$display("*** %t: cache%01d snp rsp tag=%0h", $time, CACHE_ID, snp_rsp_tag);
end
end*/
endmodule

18
hw/rtl/cache/VX_snp_forwarder.v vendored
View File

@@ -113,18 +113,18 @@ module VX_snp_forwarder #(
end
`ifdef DBG_PRINT_SNP_FWD
always_comb begin
if (1'($time & 1) && snp_req_valid && snp_req_ready) begin
$display("*** %t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag);
always_ff @(posedge clk) begin
if (snp_req_valid && snp_req_ready) begin
$display("%t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag);
end
if (1'($time & 1) && snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
$display("*** %t: snp fwd_out: addr=%0h, tag=%0h", $time, snp_fwdout_addr[0], snp_fwdout_tag[0]);
if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
$display("%t: snp fwd_out: addr=%0h, tag=%0h", $time, snp_fwdout_addr[0], snp_fwdout_tag[0]);
end
if (1'($time & 1) && fwdin_valid && fwdin_ready) begin
$display("*** %t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag);
if (fwdin_valid && fwdin_ready) begin
$display("%t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag);
end
if (1'($time & 1) && snp_rsp_valid && snp_rsp_ready) begin
$display("*** %t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
if (snp_rsp_valid && snp_rsp_ready) begin
$display("%t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
end
end
`endif