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  • bcea9866a7 Fixed a couple of things felsabbagh3 2020-04-04 18:20:06 -07:00
  • d0765b8fb1 Now Flush Routine only sends one round of snoops felsabbagh3 2020-04-04 18:02:57 -07:00
  • 65fa9285bf Fixed Flushing and Prefetching felsabbagh3 2020-04-04 17:57:35 -07:00
  • a7a1906bea Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-04-04 10:14:24 -07:00
  • 70bd673031 Resseting GPR felsabbagh3 2020-04-04 10:13:26 -07:00
  • 0a8d829f15 basic test update Blaise Tine 2020-04-04 09:07:04 -04:00
  • 07ec0ef344 OPAE hw snooping fixes Blaise Tine 2020-04-04 05:07:45 -07:00
  • 1f63139ce5 fix RTL code undefined variables Blaise Tine 2020-04-03 22:59:40 -07:00
  • 41f3245376 enable Vortex compiler to support using environment path Blaise Tine 2020-04-03 20:24:57 -04:00
  • 5e54bdffe9 POCL compiler with relative path Blaise Tine 2020-04-03 17:47:55 -04:00
  • 621e0b2a25 Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis codetector 2020-04-03 15:06:58 -04:00
  • 6ae9a6732b Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-04-03 15:04:15 -04:00
  • 9ee12d4a01 Merge branch 'fpga_synthesis' of github.gatech.edu:casl/Vortex into fpga_synthesis codetector 2020-04-03 14:36:52 -04:00
  • 10e445d459 Provisioned Prefetching, currently disabled felsabbagh3 2020-04-03 00:30:33 -07:00
  • c05ea79afa Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-04-03 00:13:46 -04:00
  • 66a879608e udpated OpenCL runtime to include cache flushing Blaise Tine 2020-04-03 00:13:24 -04:00
  • 8ad75e0442 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-04-02 20:26:46 -07:00
  • 7d1cc5234e Fixed dram_fill_accept dependant on input address felsabbagh3 2020-04-02 20:26:37 -07:00
  • ee77c76785 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-04-02 20:09:20 -07:00
  • f590d6acc8 minor update Blaise Tine 2020-04-02 20:09:08 -07:00
  • 8c1b72691f Updated head location to 9-a felsabbagh3 2020-04-02 19:41:53 -07:00
  • fbda21d5f5 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-04-02 19:38:49 -07:00
  • 478c3cf21d Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-04-02 19:19:31 -07:00
  • 0e0b326b31 Removed bank Hazard Signals felsabbagh3 2020-04-02 19:19:00 -07:00
  • 5b9ee0bb7b Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-04-02 16:01:52 -07:00
  • bc6b2969ef minor opae hw fixed Blaise Tine 2020-04-02 15:41:12 -07:00
  • 26b9fef2d8 remove binaries codetector 2020-04-02 14:20:14 -04:00
  • 00f202bddb two more benchmarks codetector 2020-03-31 15:18:11 -04:00
  • c6319a0dbd more gitignore update codetector 2020-04-02 14:16:02 -04:00
  • b9e5612949 fix gitignore codetector 2020-03-31 13:09:49 -04:00
  • abc0624086 fix makefile codetector 2020-04-02 14:13:38 -04:00
  • 299e3aa72f kmeans should compile with new loading methid codetector 2020-03-28 15:46:30 -04:00
  • 6463cca529 extending basic test Blaise Tine 2020-04-02 08:46:32 -07:00
  • efd3c1d154 udpate Blaise Tine 2020-04-02 06:51:11 -04:00
  • f7b7c509d5 udpate Blaise Tine 2020-04-02 05:16:13 -04:00
  • 7e4399e3ac OPAE HW full redesign - basic test passing Blaise Tine 2020-04-02 05:10:51 -04:00
  • 7b4b44e5ab Fixed DRAM random latency simulator felsabbagh3 2020-03-31 20:33:45 -07:00
  • 1b9d9f3625 Fixed incorrect miss_add on pipeline stall felsabbagh3 2020-03-31 20:23:09 -07:00
  • bca5ac5e7f enable rtl sim dram stalls Blaise Tine 2020-03-31 02:41:14 -04:00
  • e92c4b6774 enable rtl sim dram stalls Blaise Tine 2020-03-31 02:38:18 -04:00
  • ba8bc95c90 Newlib update felsabbagh3 2020-03-30 23:08:38 -07:00
  • bcf894b581 Demo SOC W=8, T=4 Passing felsabbagh3 2020-03-30 22:17:38 -07:00
  • 66a837b0df SOC only 2 errors felsabbagh3 2020-03-30 21:28:40 -07:00
  • 88f2ad53d0 Fixed simulator includes felsabbagh3 2020-03-30 16:43:26 -07:00
  • f6eb5dfbae refactor RTL sim, added DRAM stalls support Blaise Tine 2020-03-30 04:13:19 -04:00
  • 638625184f Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-03-29 23:46:44 -07:00
  • ff2b8dba12 Fixed req_addr width felsabbagh3 2020-03-29 23:46:38 -07:00
  • 0f39d0fcbd Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-03-30 01:53:53 -04:00
  • 2eb19e23c2 refactor RTL simulator Blaise Tine 2020-03-30 01:53:34 -04:00
  • ccc65a06fe Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-03-29 21:22:08 -07:00
  • 36895d6e7c Fixed miss_add on for snoop replays felsabbagh3 2020-03-29 21:21:53 -07:00
  • 2d198a32c7 update Blaise Tine 2020-03-29 23:18:26 -04:00
  • 94cc2c10b1 Snoops shouldn't send fill requests felsabbagh3 2020-03-29 19:16:00 -07:00
  • e31b2d6d7e Fixed pulling signals from different stages felsabbagh3 2020-03-29 18:17:01 -07:00
  • d31116d584 Uses use_wb_valid instead of wb_req to include snoops felsabbagh3 2020-03-29 17:59:10 -07:00
  • 71aae3e0a9 .. felsabbagh3 2020-03-29 17:28:57 -07:00
  • f96d77d75e Mismatched vs matched felsabbagh3 2020-03-29 17:18:57 -07:00
  • a499bcd718 Added extra signals for debugging felsabbagh3 2020-03-29 17:04:17 -07:00
  • 95ee66f25a Fixed Snoop Invalidate Logic felsabbagh3 2020-03-29 16:44:14 -07:00
  • 73390b9f58 b/unb error felsabbagh3 2020-03-29 16:09:48 -07:00
  • 0a88c97485 Another reset issue... felsabbagh3 2020-03-29 16:06:13 -07:00
  • b99ba2c413 Removed scheduler_empty qualifier felsabbagh3 2020-03-29 15:24:50 -07:00
  • eb6e0cee43 Fixing a bug in a fix... felsabbagh3 2020-03-29 13:52:22 -07:00
  • cd418a1f96 Mrvq stopping reqq popping added to avoid mrvq full deadlock felsabbagh3 2020-03-29 13:19:06 -07:00
  • f43a9ad1a6 Added proper resetting to cache felsabbagh3 2020-03-29 10:57:32 -07:00
  • 3a23e05a88 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-03-29 05:24:48 -04:00
  • ce0cc44d11 update Blaise Tine 2020-03-29 05:24:40 -04:00
  • 2c75b7e800 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-03-29 02:11:23 -07:00
  • efac643c66 Added Proper Handshaking to Everything and Fixed a Couple of Bugs felsabbagh3 2020-03-29 02:11:14 -07:00
  • ede41dff1b Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis Blaise Tine 2020-03-29 01:17:32 -04:00
  • c57de94b5c minor update Blaise Tine 2020-03-29 01:17:09 -04:00
  • d31b607e01 Merge branch 'fpga_synthesis' of https://github.gatech.edu/casl/Vortex into fpga_synthesis felsabbagh3 2020-03-28 21:43:51 -07:00
  • 313a8e3b4b All cache bugs fixed - Handshaking felsabbagh3 2020-03-28 21:43:02 -07:00
  • 002d8fbec9 minor update Blaise Tine 2020-03-29 00:40:02 -04:00
  • c8a6470595 redesigned driver demo, fixed startup code, removed --cpu from simx, Blaise Tine 2020-03-29 00:38:17 -04:00
  • 2d5cf89e00 update Blaise Tine 2020-03-28 02:40:38 -04:00
  • 17625e7709 update Blaise Tine 2020-03-28 01:43:26 -04:00
  • 22be51b0c8 fixed multicore build Blaise Tine 2020-03-28 01:40:26 -04:00
  • cff762c435 adding opencl runtime and compiler tools Blaise Tine 2020-03-28 00:35:54 -04:00
  • 5dc9493c61 ALL tests passing - handshake felsabbagh3 2020-03-27 21:34:49 -07:00
  • f7e0d1e491 missing runtime changes from OPAE Blaise Tine 2020-03-27 22:51:54 -04:00
  • 96e960fa69 missing runtime changes from OPAE Blaise Tine 2020-03-27 22:51:54 -04:00
  • 89d5bfbef1 missing simX changes from OPAE Blaise Tine 2020-03-27 22:44:16 -04:00
  • f3889f8744 missing simX changes from OPAE Blaise Tine 2020-03-27 22:44:16 -04:00
  • e80fa7f233 missing rtl changes from OPAE Blaise Tine 2020-03-27 22:37:35 -04:00
  • 8bb1f66220 missing rtl changes from OPAE Blaise Tine 2020-03-27 22:37:35 -04:00
  • 550d96a73c rtlsim driver works with Vortex! Blaise Tine 2020-03-27 21:54:55 -04:00
  • e43f5c8767 rtlsim driver works with Vortex! Blaise Tine 2020-03-27 21:54:55 -04:00
  • 5d320a9313 fixed multicore build Blaise Tine 2020-03-27 21:04:23 -04:00
  • 2ed7bd3755 fixed multicore build Blaise Tine 2020-03-27 21:04:23 -04:00
  • 51fd8974a9 minor build fixes Blaise Tine 2020-03-27 20:56:18 -04:00
  • 2415199a8c minor build fixes Blaise Tine 2020-03-27 20:56:18 -04:00
  • 5a5c9f3981 merging changes from OPAE branch making this branch Blaise Tine 2020-03-27 20:19:16 -04:00
  • 9b1b8789ac merging changes from OPAE branch making this branch Blaise Tine 2020-03-27 20:19:16 -04:00
  • 614797e52f Migrating fpga_synthesis_temp to main felsabbagh3 2020-03-27 13:15:23 -07:00
  • 39516a6f98 Migrating fpga_synthesis_temp to main felsabbagh3 2020-03-27 13:15:23 -07:00
  • 6dc3d0d371 refactor VX_define.v Blaise Tine 2020-03-27 13:56:16 -04:00
  • d54ba1e9ae refactor VX_define.v Blaise Tine 2020-03-27 13:56:16 -04:00
  • 3df21b6e71 fixed regression bug with Vortex.v model hanging issue Blaise Tine 2020-03-27 13:19:11 -04:00
  • 4eb8769423 fixed regression bug with Vortex.v model hanging issue Blaise Tine 2020-03-27 13:19:11 -04:00