Blaise Tine
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bb1ceffadd
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rebase master update
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2021-07-30 21:03:14 -07:00 |
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b6596494ff
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minor update
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2021-07-30 15:50:04 -07:00 |
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7807e285ac
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minor update
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2021-07-27 00:30:10 -07:00 |
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b307c40ae7
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mshr critical path optimization
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2021-07-26 21:11:17 -07:00 |
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ea1e0f201e
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OUTPUT_REG refactoring
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2021-07-23 06:58:37 -07:00 |
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1f94a1e673
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minor update
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2021-07-22 14:11:59 -07:00 |
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b3e54a837e
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minor update
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2021-07-20 12:01:04 -07:00 |
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53b3d42908
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cache's core response queue size control
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2021-07-16 13:09:29 -07:00 |
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f54d2b6272
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minor update
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2021-07-15 14:39:41 -07:00 |
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0bec734532
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icache readonly optimization
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2021-07-15 14:16:05 -07:00 |
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d9425cc484
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cache elastic buffer optimization
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2021-07-15 11:59:49 -07:00 |
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8678150ce0
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cache multi-porting optimization
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2021-07-15 11:54:27 -07:00 |
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f57fa82028
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cache bank select optimization
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2021-07-15 11:42:17 -07:00 |
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22cf698e69
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minor update
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2021-07-13 05:25:44 -07:00 |
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Blaise Tine
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6bcf999125
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non-cacheable address bypass optimization
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2021-07-13 05:21:57 -07:00 |
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5c40422e4f
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dcache response bus optimization
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2021-07-12 10:14:48 -07:00 |
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10e9ee124b
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using onehot multiplexer to reduce critical path
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2021-07-08 00:26:59 -07:00 |
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Blaise Tine
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dc34c5c5bd
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minor update
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2021-07-03 04:47:19 -07:00 |
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Blaise Tine
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f84c8a0b5d
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instr_sched => ibuffer
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2021-06-27 19:36:43 -07:00 |
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1ea738ed26
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lkg build
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2021-06-25 16:28:10 -07:00 |
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57143f5889
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synthesis optimizations
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2021-06-17 16:43:43 -07:00 |
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47c3234659
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minor update
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2021-06-13 10:58:48 -07:00 |
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Blaise Tine
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8bf85c1983
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fixed non-cacheable memory with l2 cache
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2021-06-10 15:11:37 -07:00 |
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Blaise Tine
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adf033b0aa
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non-cacheable memory address critical paths optimizations
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2021-06-10 12:47:18 -07:00 |
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Blaise Tine
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41069ba188
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non-cacheable memory address fixes
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2021-06-06 20:54:36 -07:00 |
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Blaise Tine
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3071fb7a29
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adding support for non-cacheable memory addressing
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2021-06-06 13:35:55 -07:00 |
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Blaise Tine
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5d2437d887
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refactoring cache_config
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2021-05-27 14:41:46 -07:00 |
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Blaise Tine
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4c5104e96a
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fixed shared memory multi-tag requests bug
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2021-05-26 15:03:48 -07:00 |
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Blaise Tine
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d8517d4d08
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minor update
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2021-05-26 13:37:07 -07:00 |
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Blaise Tine
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244f4b0964
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fixed shared memory write bug
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2021-05-23 10:57:58 -07:00 |
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04a1c0e9eb
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IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
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2021-05-01 13:44:08 -07:00 |
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8410c49f53
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code refactoring: DRAM => MEM renaming
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2021-04-26 00:58:48 -07:00 |
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d808aa2735
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perf counters generic size
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2021-04-25 21:15:24 -07:00 |
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4cb98a25a7
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enabling 128-bit dram bus
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2021-04-24 00:31:27 -04:00 |
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aff5903a22
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minor ibuffer critical path optimization.
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2021-04-19 20:53:13 -07:00 |
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Blaise Tine
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625689796f
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minor update
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2021-04-04 23:42:57 -07:00 |
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Blaise Tine
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d6552a8851
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minor update
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2021-04-03 04:24:37 -07:00 |
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Blaise Tine
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04a96e89c9
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minor update
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2021-04-01 12:34:18 -07:00 |
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062d02ddce
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Merge branch 'master' of https://github.gatech.edu/casl/Vortex
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2021-03-04 20:51:03 -08:00 |
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Blaise Tine
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3f5fd6d394
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using shiftreg-based skid buffers
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2021-02-28 02:20:09 -08:00 |
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e64996946d
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using 44-bit perf counters - aligned with DSP counters width
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2021-02-28 02:05:47 -08:00 |
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Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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1346d64ba9
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minor update
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2021-02-22 04:04:13 -08:00 |
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Blaise Tine
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7560202f8b
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cache bank refactoring - removing unecessary core response fifo & restoring single port data access
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2021-02-21 21:47:46 -08:00 |
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Blaise Tine
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ccb74ef286
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cache data access with decoupled read/write ports
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2021-02-21 15:18:24 -08:00 |
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Blaise Tine
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05f93fac20
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minor update
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2021-02-20 13:15:15 -08:00 |
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Blaise Tine
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9eed48435c
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instruction decode optimization
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2021-02-14 00:19:54 -08:00 |
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Blaise Tine
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3c37db877a
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cache specialization for in-order DRAM reponses
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2021-02-13 20:23:29 -08:00 |
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Blaise Tine
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ab63ac9e5d
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cache request interfaces update
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2021-02-10 20:55:04 -08:00 |
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Blaise Tine
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665b97b810
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multi-ported cache support for streaming
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2021-02-08 16:13:32 -08:00 |
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