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minor update

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This commit is contained in:
Blaise Tine
2021-07-03 04:47:19 -07:00
parent 360f8e4e37
commit dc34c5c5bd
5 changed files with 29 additions and 51 deletions
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13
hw/rtl/VX_ibuffer.v
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@@ -110,10 +110,11 @@ module VX_ibuffer #(
// schedule the next instruction to issue
always @(*) begin
deq_valid_n = enq_fire;
deq_wid_n = decode_if.wid;
deq_instr_n = q_data_in;
if (num_warps > 1) begin
deq_valid_n = 1;
deq_wid_n = 'x;
deq_instr_n = 'x;
for (integer i = `NUM_WARPS-1; i >= 0; --i) begin
if (schedule_table[i]) begin
deq_wid_n = `NW_BITS'(i);
@@ -124,17 +125,12 @@ module VX_ibuffer #(
deq_valid_n = 1;
deq_wid_n = deq_wid;
deq_instr_n = deq_fire ? q_data_prev[deq_wid] : q_data_out[deq_wid];
end else begin
deq_valid_n = enq_fire;
deq_wid_n = decode_if.wid;
deq_instr_n = q_data_in;
end
end
// do round-robin scheduling with multiple active warps
always @(*) begin
if (1 == $countones(schedule_table)
|| (num_warps < 2)) begin
if ($countones(schedule_table) <= 1) begin
schedule_table_n = valid_table_n;
end else begin
schedule_table_n = schedule_table;
@@ -150,6 +146,7 @@ module VX_ibuffer #(
valid_table <= 0;
deq_valid <= 0;
num_warps <= 0;
schedule_table <= 0;
end else begin
valid_table <= valid_table_n;
deq_valid <= deq_valid_n;

39
hw/rtl/cache/VX_nc_bypass.v vendored
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@@ -264,36 +264,21 @@ module VX_nc_bypass #(
if (NUM_REQS > 1) begin
wire [CORE_REQ_TIDW-1:0] rsp_tid = mem_rsp_tag_in[(CORE_TAG_WIDTH + D) +: CORE_REQ_TIDW];
if (NUM_RSP_TAGS > 1) begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 0;
core_rsp_valid_out_r[rsp_tid] = 1;
for (integer i = 0; i < NUM_REQS; ++i) begin
core_rsp_tag_out_r[i] = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
end
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
core_rsp_tag_out_r = core_rsp_tag_in;
core_rsp_ready_in_r = core_rsp_ready_out;
end
end
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 0;
core_rsp_valid_out_r[rsp_tid] = 1;
core_rsp_tag_out_r = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
core_rsp_tag_out_r = core_rsp_tag_in;
core_rsp_ready_in_r = core_rsp_ready_out;
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 0;
core_rsp_valid_out_r[rsp_tid] = 1;
for (integer i = 0; i < NUM_RSP_TAGS; ++i) begin
core_rsp_tag_out_r[i] = mem_rsp_tag_in[CORE_TAG_WIDTH-1:0];
end
core_rsp_ready_in_r = 0;
end else begin
core_rsp_valid_out_r = core_rsp_valid_in;
core_rsp_tag_out_r = core_rsp_tag_in;
core_rsp_ready_in_r = core_rsp_ready_out;
end
end
end else begin
end else begin
always @(*) begin
if (is_mem_rsp_nc) begin
core_rsp_valid_out_r = 1;

2
hw/rtl/libs/VX_onehot_encoder.v
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@@ -60,7 +60,7 @@ module VX_onehot_encoder #(
end
assign data_out = addr[levels_lp][`LOG2UP(N)-1:0];
assign valid = (| data_in);
assign valid = v[levels_lp][0];
`IGNORE_WARNINGS_END
end else begin

2
hw/rtl/libs/VX_priority_encoder.v
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@@ -87,7 +87,7 @@ module VX_priority_encoder #(
assign index = index_r;
assign onehot = onehot_r;
assign valid_out = (| data_in);
assign valid_out = (| data_in);
end

24
hw/rtl/libs/VX_stream_arbiter.v
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@@ -22,10 +22,10 @@ module VX_stream_arbiter #(
localparam LOG_NUM_REQS = $clog2(NUM_REQS);
if (NUM_REQS > 1) begin
wire sel_enable;
wire sel_valid;
wire sel_ready;
wire [LOG_NUM_REQS-1:0] sel_idx;
wire [NUM_REQS-1:0] sel_1hot;
wire [NUM_REQS-1:0] sel_1hot;
if (TYPE == "X") begin
VX_fixed_arbiter #(
@@ -35,7 +35,7 @@ module VX_stream_arbiter #(
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
@@ -48,7 +48,7 @@ module VX_stream_arbiter #(
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
@@ -61,7 +61,7 @@ module VX_stream_arbiter #(
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
@@ -74,7 +74,7 @@ module VX_stream_arbiter #(
.clk (clk),
.reset (reset),
.requests (valid_in),
.enable (sel_enable),
.enable (sel_ready),
.grant_valid (sel_valid),
.grant_index (sel_idx),
.grant_onehot (sel_1hot)
@@ -83,8 +83,6 @@ module VX_stream_arbiter #(
$error ("invalid parameter");
end
wire ready_in_sel;
VX_skid_buffer #(
.DATAW (DATAW),
.PASSTHRU (!BUFFERED)
@@ -93,17 +91,15 @@ module VX_stream_arbiter #(
.reset (reset),
.valid_in (sel_valid),
.data_in (data_in[sel_idx]),
.ready_in (ready_in_sel),
.ready_in (sel_ready),
.valid_out (valid_out),
.data_out (data_out),
.ready_out (ready_out)
);
assign sel_enable = ready_in_sel;
for (genvar i = 0; i < NUM_REQS; i++) begin
assign ready_in[i] = sel_1hot[i] && ready_in_sel;
end
assign ready_in[i] = sel_1hot[i] && sel_ready;
end
end else begin
@@ -112,7 +108,7 @@ module VX_stream_arbiter #(
assign valid_out = valid_in;
assign data_out = data_in;
assign ready_in = ready_out;
assign ready_in = ready_out;
end