wgulian3
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8318aff69f
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Support exec multi-cycle for div/mul
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2020-02-13 13:17:46 -05:00 |
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wgulian3
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c1bd731d7f
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Add ram async clear port fix for fpga RAM inference
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2020-02-06 13:07:50 -05:00 |
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wgulian3
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9c7a9d88cf
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Replace div/rem expressions with divider modules in preparation for pipelining
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2020-02-04 11:54:06 -05:00 |
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wgulian3
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0211ca4add
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Add compat divide module and tb
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2020-02-04 10:59:05 -05:00 |
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wgulian3
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8d20b52ea2
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Cleanup imports of VX_define
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2020-02-04 10:57:32 -05:00 |
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wgulian3
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d727404f3b
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timing analysis tcl
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2020-01-28 04:09:00 -05:00 |
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wgulian3
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4158b29f29
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Fancier SDC file
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2020-01-28 02:20:13 -05:00 |
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wgulian3
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a6e74f589e
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Update files
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2020-01-27 20:35:45 -05:00 |
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wgulian3
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12a4136464
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quartus makefile: Support custom Quartus root location
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2020-01-24 18:42:03 -05:00 |
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wgulian3
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e9cdc6e5af
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SystemVerilog tweaks to appease Quartus and make Quartus synthesis work
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2020-01-24 06:10:24 -05:00 |
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Lyons, Ethan Tyler
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b583e206a2
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Fixed GPR Stage to be Generic when ASIC is defined
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2019-11-22 09:20:20 -05:00 |
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fares
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9e58bf8fb5
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Started synthesis script
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2019-11-22 00:32:19 -05:00 |
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fares
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d4f6a7e3b2
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reverted to 4 thread configuration
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2019-11-22 00:13:55 -05:00 |
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fares
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8acc32372b
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8Warp 32Threads for GTCAD synthesis
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2019-11-21 23:51:11 -05:00 |
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fares
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c4d315dfed
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VCD for power
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2019-11-21 23:25:51 -05:00 |
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Lyons, Ethan Tyler
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c8abd48458
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Synthesis Compatible
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2019-11-21 21:42:34 -05:00 |
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Lyons, Ethan Tyler
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b748a7665d
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Synthesis Compatible
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2019-11-21 21:41:41 -05:00 |
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Lyons, Ethan Tyler
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e56e42c8c3
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Synthesis Compatible
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2019-11-21 21:41:11 -05:00 |
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Lyons, Ethan Tyler
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52e881243e
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Warps/Threads Parameterization
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2019-11-21 01:15:54 -05:00 |
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Lyons, Ethan Tyler
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9f58584207
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Warps/Threads Parameterization
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2019-11-21 01:15:21 -05:00 |
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Lyons, Ethan Tyler
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509850192c
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Warps/Threads Parameterization
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2019-11-21 01:14:50 -05:00 |
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fares
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c09a15069b
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Improving critical path
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2019-11-18 13:11:05 -05:00 |
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fares
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c6d56f11c3
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Added EXEC to Warp Scheduler buffer
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2019-11-18 11:34:51 -05:00 |
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fares
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53c78b905a
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Switched to g++
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2019-11-16 12:23:59 -05:00 |
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fares
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19dba43849
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vecadd bug fixing + ebreak for termination
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2019-11-15 14:18:45 -05:00 |
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fares
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3d5120640b
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clCreateProgramWithBuiltInKernels OpenCL Error
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2019-11-15 01:14:31 -05:00 |
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felsabbagh3
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70651f0340
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Added a pipeline stage + fixed SM param errors
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2019-11-13 12:25:28 -05:00 |
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Lyons, Ethan Tyler
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7f7d17d176
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Shared Memory Implemented
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2019-11-13 10:06:36 -05:00 |
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Lyons, Ethan Tyler
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2994e607e3
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Shared Memory Implemented
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2019-11-13 10:06:13 -05:00 |
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felsabbagh3
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25647b46df
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Fixed SM simple
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2019-11-13 02:15:18 -05:00 |
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felsabbagh3
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b67ba1881b
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Fixed valid signal
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2019-11-13 01:58:04 -05:00 |
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felsabbagh3
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ef83285c6c
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FileIO Schema started
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2019-11-12 00:31:30 -05:00 |
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felsabbagh3
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7ed88ce4c1
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Fixed AA d_cache sizing errors
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2019-11-11 15:20:58 -05:00 |
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felsabbagh3
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4b2ea58b79
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Syn prep
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2019-11-11 14:20:15 -05:00 |
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felsabbagh3
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92e88a7bb2
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Fixed cache meta
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2019-11-10 15:38:39 -05:00 |
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felsabbagh3
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31de18c328
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Changed tb
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2019-11-10 15:06:06 -05:00 |
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felsabbagh3
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b3c7ac435a
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added sm defines
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2019-11-10 14:01:54 -05:00 |
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felsabbagh3
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fbf708e419
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Started simX
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2019-11-10 01:21:09 -05:00 |
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felsabbagh3
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ea7bd485ca
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Icache/Dcache finally done + configurability tested:
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2019-11-09 00:03:15 -05:00 |
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felsabbagh3
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8b81989bfd
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Before way logic change
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2019-11-08 18:16:40 -05:00 |
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Lyons, Ethan Tyler
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c79d08e12c
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Add files via upload
ICache_In_Place
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2019-11-08 10:56:44 -05:00 |
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Lyons, Ethan Tyler
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1c21110ffe
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Add files via upload
ICache_In_Place
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2019-11-08 10:56:11 -05:00 |
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Lyons, Ethan Tyler
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6c4cd2468f
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Add files via upload
ICache_In_Place
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2019-11-08 10:55:35 -05:00 |
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Lyons, Ethan Tyler
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b0f685c2e2
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Add files via upload
ICache_In_Place
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2019-11-08 10:55:08 -05:00 |
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felsabbagh3
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5d5ad9c4ec
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FIXED BUGS
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2019-11-07 13:54:46 -05:00 |
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felsabbagh3
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58a9140f08
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Before evict_wb_old removal
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2019-11-07 13:27:38 -05:00 |
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Savan Roshan
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e4ee2a9cbd
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Parameterization working
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2019-11-07 00:14:46 -05:00 |
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felsabbagh3
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9e2de897f0
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Added simple_main
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2019-11-07 00:10:06 -05:00 |
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Savan Roshan
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cb1bf65017
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Parameterization working
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2019-11-06 11:12:27 -05:00 |
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Savan Roshan
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3a71a2ebdb
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Fixed bugs in parameterization
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2019-11-06 01:09:30 -05:00 |
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