Syn prep

rtl/VX_define.v

@@ -9,7 +9,7 @@
 // Uncomment the below line if NW=1
 // `define ONLY
 
-// `define SYN 1
+`define SYN 1
 `define ASIC 1
 
 `define NUM_BARRIERS 4

rtl/VX_gpr.v

@@ -63,6 +63,7 @@ module VX_gpr (
 		wire[`NT_M1:0][31:0] temp_b;
 
 
+		`ifndef SYN
 			genvar thread;
 			genvar curr_bit;
 			for (thread = 0; thread < `NT; thread = thread + 1)
@@ -74,6 +75,13 @@ module VX_gpr (
 				end
 			end
 
+		`else
+
+		assign out_a_reg_data = temp_a;
+		assign out_b_reg_data = temp_b;
+
+		`endif 
+
 
 		wire[`NT_M1:0][31:0] to_write = (VX_writeback_inter.rd != 0) ? VX_writeback_inter.write_data : 0;