Added EXEC to Warp Scheduler buffer
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@@ -86,7 +86,8 @@ VX_lsu load_store_unit(
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VX_execute_unit VX_execUnit(
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// .clk (clk),
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.clk (clk),
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.reset (reset),
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.VX_exec_unit_req(VX_exec_unit_req),
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.VX_inst_exec_wb (VX_inst_exec_wb),
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.VX_jal_rsp (VX_jal_rsp),
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@@ -1,8 +1,8 @@
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`include "VX_define.v"
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module VX_execute_unit (
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// input wire clk,
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// Input
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input wire clk,
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input wire reset,
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// Request
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VX_exec_unit_req_inter VX_exec_unit_req,
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@@ -95,6 +95,13 @@ module VX_execute_unit (
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end
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endgenerate
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// VX_inst_exec_wb_inter VX_inst_exec_wb_temp();
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// JAL Response
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VX_jal_response_inter VX_jal_rsp_temp();
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// Branch Response
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VX_branch_response_inter VX_branch_rsp_temp();
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// Actual Writeback
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assign VX_inst_exec_wb.rd = VX_exec_unit_req.rd;
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assign VX_inst_exec_wb.wb = VX_exec_unit_req.wb;
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@@ -104,17 +111,46 @@ module VX_execute_unit (
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assign VX_inst_exec_wb.exec_wb_pc = in_curr_PC;
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// Jal rsp
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assign VX_jal_rsp.jal = in_jal;
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assign VX_jal_rsp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
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assign VX_jal_rsp.jal_warp_num = VX_exec_unit_req.warp_num;
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assign VX_jal_rsp_temp.jal = in_jal;
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assign VX_jal_rsp_temp.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset);
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assign VX_jal_rsp_temp.jal_warp_num = VX_exec_unit_req.warp_num;
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// Branch rsp
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assign VX_branch_rsp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid);
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assign VX_branch_rsp.branch_dir = temp_branch_dir;
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assign VX_branch_rsp.branch_warp_num = VX_exec_unit_req.warp_num;
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assign VX_branch_rsp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset
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assign VX_branch_rsp_temp.valid_branch = (VX_exec_unit_req.branch_type != `NO_BRANCH) && (|VX_exec_unit_req.valid);
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assign VX_branch_rsp_temp.branch_dir = temp_branch_dir;
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assign VX_branch_rsp_temp.branch_warp_num = VX_exec_unit_req.warp_num;
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assign VX_branch_rsp_temp.branch_dest = $signed(VX_exec_unit_req.curr_PC) + ($signed(VX_exec_unit_req.itype_immed) << 1); // itype_immed = branch_offset
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wire zero = 0;
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// VX_generic_register #(.N(174)) exec_reg(
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// .clk (clk),
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// .reset(reset),
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// .stall(zero),
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// .flush(zero),
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// .in ({VX_inst_exec_wb_temp.rd, VX_inst_exec_wb_temp.wb, VX_inst_exec_wb_temp.wb_valid, VX_inst_exec_wb_temp.wb_warp_num, VX_inst_exec_wb_temp.alu_result, VX_inst_exec_wb_temp.exec_wb_pc}),
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// .out ({VX_inst_exec_wb.rd , VX_inst_exec_wb.wb , VX_inst_exec_wb.wb_valid , VX_inst_exec_wb.wb_warp_num , VX_inst_exec_wb.alu_result , VX_inst_exec_wb.exec_wb_pc })
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// );
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VX_generic_register #(.N(36)) jal_reg(
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.clk (clk),
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.reset(reset),
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.stall(zero),
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.flush(zero),
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.in ({VX_jal_rsp_temp.jal, VX_jal_rsp_temp.jal_dest, VX_jal_rsp_temp.jal_warp_num}),
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.out ({VX_jal_rsp.jal , VX_jal_rsp.jal_dest , VX_jal_rsp.jal_warp_num})
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);
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VX_generic_register #(.N(37)) branch_reg(
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.clk (clk),
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.reset(reset),
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.stall(zero),
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.flush(zero),
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.in ({VX_branch_rsp_temp.valid_branch, VX_branch_rsp_temp.branch_dir, VX_branch_rsp_temp.branch_warp_num, VX_branch_rsp_temp.branch_dest}),
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.out ({VX_branch_rsp.valid_branch , VX_branch_rsp.branch_dir , VX_branch_rsp.branch_warp_num , VX_branch_rsp.branch_dest })
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);
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// always @(*) begin
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// case(in_alu_op)
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// `CSR_ALU_RW: out_csr_result = in_csr_mask;
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@@ -38,10 +38,10 @@ module VX_shared_memory_block
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//for (curr_ind = 0; curr_ind < 128; curr_ind = curr_ind + 1)
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for (curr_ind = 0; curr_ind < SMB_HEIGHT; curr_ind = curr_ind + 1)
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begin
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shared_memory[curr_ind] <= 0;
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shared_memory[curr_ind] = 0;
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end
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end else if(shm_write) begin
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shared_memory[addr][we][31:0] <= wdata[we][31:0]; // - Ethan's addition
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shared_memory[addr][we][31:0] = wdata[we][31:0]; // - Ethan's addition
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//if (we == 2'b00) shared_memory[addr][0][31:0] <= wdata[0][31:0];
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//if (we == 2'b01) shared_memory[addr][1][31:0] <= wdata[1][31:0];
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//if (we == 2'b10) shared_memory[addr][2][31:0] <= wdata[2][31:0];
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