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Before way logic change

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This commit is contained in:
felsabbagh3
2019-11-08 18:16:40 -05:00
parent c79d08e12c
commit 8b81989bfd
9 changed files with 314 additions and 442 deletions
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26
rtl/VX_define.v
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@@ -128,20 +128,24 @@
//Cache configurations
//Cache configurations
`define ICACHE_SIZE 4096 //Bytes
//Bytes
`define ICACHE_SIZE 1024
`ifdef SYN
`define ICACHE_WAYS 1
`else
`define ICACHE_WAYS 2
`endif
`define ICACHE_BLOCK 128 //Bytes
//Bytes
`define ICACHE_BLOCK 8
`define ICACHE_BANKS 1
`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS)
`define ICACHE_NUM_WORDS_PER_BLOCK 16
`define ICACHE_NUM_WORDS_PER_BLOCK (`ICACHE_BLOCK / (`ICACHE_BANKS * 4))
`define ICACHE_NUM_REQ 1
`define ICACHE_LOG_NUM_REQ `CLOG2(`ICACHE_NUM_REQ)
`define ICACHE_WAY_INDEX `CLOG2(`ICACHE_WAYS) //set this to 1 if CACHE_WAYS is 1
//set this to 1 if CACHE_WAYS is 1
`define ICACHE_WAY_INDEX `CLOG2(`ICACHE_WAYS)
//`define ICACHE_WAY_INDEX 1
`define ICACHE_BLOCK_PER_BANK (`ICACHE_BLOCK / `ICACHE_BANKS)
@@ -180,20 +184,24 @@
`define ICACHE_ADDR_TAG_END 31
//Cache configurations
`define DCACHE_SIZE 4096 //Bytes
//Bytes
`define DCACHE_SIZE 4096
`ifdef SYN
`define DCACHE_WAYS 1
`else
`define DCACHE_WAYS 4
`define DCACHE_WAYS 2
`endif
`define DCACHE_BLOCK 128 //Bytes
//Bytes
`define DCACHE_BLOCK 64
`define DCACHE_BANKS 4
`define DCACHE_LOG_NUM_BANKS $clog2(`DCACHE_BANKS)
`define DCACHE_NUM_WORDS_PER_BLOCK 4
`define DCACHE_NUM_WORDS_PER_BLOCK (`DCACHE_BLOCK / (`DCACHE_BANKS * 4))
`define DCACHE_NUM_REQ `NT
`define DCACHE_LOG_NUM_REQ $clog2(`DCACHE_NUM_REQ)
`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS) //set this to 1 if CACHE_WAYS is 1
//set this to 1 if CACHE_WAYS is 1
`define DCACHE_WAY_INDEX $clog2(`DCACHE_WAYS)
//`define DCACHE_WAY_INDEX 1
`define DCACHE_BLOCK_PER_BANK (`DCACHE_BLOCK / `DCACHE_BANKS)

6
rtl/VX_fetch.v
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@@ -26,6 +26,7 @@ module VX_fetch (
wire[`NT_M1:0] thread_mask;
wire[`NW_M1:0] warp_num;
wire[31:0] warp_pc;
wire scheduled_warp;
VX_warp_scheduler warp_scheduler(
.clk (clk),
.reset (reset),
@@ -78,7 +79,8 @@ module VX_fetch (
.thread_mask (thread_mask),
.warp_num (warp_num),
.warp_pc (warp_pc),
.out_ebreak (out_ebreak)
.out_ebreak (out_ebreak),
.scheduled_warp (scheduled_warp)
);
// always @(*) begin
@@ -86,7 +88,7 @@ module VX_fetch (
// end
assign icache_request.pc_address = warp_pc;
assign icache_request.out_cache_driver_in_valid = !schedule_delay;
assign icache_request.out_cache_driver_in_valid = !schedule_delay && scheduled_warp;
assign icache_request.out_cache_driver_in_mem_read = `LW_MEM_READ;
assign icache_request.out_cache_driver_in_mem_write = `NO_MEM_WRITE;
assign icache_request.out_cache_driver_in_data = 32'b0;

4
rtl/VX_warp_scheduler.v
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@@ -53,7 +53,8 @@ module VX_warp_scheduler (
output wire[`NT_M1:0] thread_mask,
output wire[`NW_M1:0] warp_num,
output wire[31:0] warp_pc,
output wire out_ebreak
output wire out_ebreak,
output wire scheduled_warp
);
@@ -278,6 +279,7 @@ module VX_warp_scheduler (
assign global_stall = (stall || wstall_this_cycle || hazard || !real_schedule || is_join);
assign scheduled_warp = !(wstall_this_cycle || hazard || !real_schedule || is_join);
wire real_use_wspawn = use_wsapwn[warp_to_schedule];

21
rtl/cache/VX_cache_data_per_index.v vendored
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@@ -46,7 +46,7 @@ module VX_cache_data_per_index
wire [CACHE_WAYS-1:0] valid_use_per_way;
wire [CACHE_WAYS-1:0] dirty_use_per_way;
wire [CACHE_WAYS-1:0] hit_per_way;
reg [NUM_IND-1:0][CACHE_WAY_INDEX-1:0] eviction_way_index;
reg [CACHE_WAY_INDEX-1:0] eviction_way_index;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][3:0] we_per_way;
wire [CACHE_WAYS-1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] data_write_per_way;
wire [CACHE_WAYS-1:0] write_from_mem_per_way;
@@ -89,11 +89,11 @@ module VX_cache_data_per_index
wire update = |we && !miss;
wire valid = &valid_use_per_way;
assign way = hit ? way_index : (valid ? eviction_way_index[addr] : (invalid_found ? invalid_index : 0));
assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index[addr]] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index[addr]] : (invalid_found ? data_use_per_way[invalid_index] : 0));
assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index[addr]] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index[addr]] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
assign way = hit ? way_index : (valid ? eviction_way_index : (invalid_found ? invalid_index : 0));
assign tag_use = hit ? tag_use_per_way[way_index] : (valid ? tag_use_per_way[eviction_way_index] : (invalid_found ? tag_use_per_way[invalid_index] : 0));
assign data_use = hit ? data_use_per_way[way_index] : (valid ? data_use_per_way[eviction_way_index] : (invalid_found ? data_use_per_way[invalid_index] : 0));
assign valid_use = hit ? valid_use_per_way[way_index] : (valid ? valid_use_per_way[eviction_way_index] : (invalid_found ? valid_use_per_way[invalid_index] : 0));
assign dirty_use = hit ? dirty_use_per_way[way_index] : (valid ? dirty_use_per_way[eviction_way_index] : (invalid_found ? dirty_use_per_way[invalid_index] : 0));
@@ -132,11 +132,12 @@ module VX_cache_data_per_index
if (rst) begin
eviction_way_index <= 0;
end else begin
if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
if((eviction_way_index[addr]+1) == CACHE_WAYS) begin
eviction_way_index[addr] <= 0;
// if((miss && dirty_use && valid_use && !evict && valid_in)) begin // can be either evict or invalid cache entries
if((state == SEND_MEM_REQ)) begin // can be either evict or invalid cache entries
if((eviction_way_index+1) == CACHE_WAYS) begin
eviction_way_index <= 0;
end else begin
eviction_way_index[addr] <= (eviction_way_index[addr] + 1);
eviction_way_index <= (eviction_way_index + 1);
end
end
end