wu-arch/vortex
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fixed bugs in parameterization

Browse Source
This commit is contained in:
Savan Roshan
2019-11-06 01:09:30 -05:00
parent fcd3bbc4a1
commit 3a71a2ebdb
5 changed files with 84 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
rtl/VX_define.v
View File

@@ -12,12 +12,6 @@
// `define SYN 1
`define ASIC 1
`define DCACHE_NUM_BANKS 8
`define DCACHE_NUMBER_BANKS 8
`define DCACHE_NUM_WORDS_PER_BLOCK 4
`define NUM_BARRIERS 4
`define R_INST 7'd51
@@ -139,7 +133,7 @@
// Offset
`define DCACHE_OFFSET_NB ($clog2(`DCACHE_NUM_WORDS_PER_BLOCK))
`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_NUMBER_BANKS))
`define DCACHE_OFFSET_ST (2+$clog2(`DCACHE_BANKS))
`define DCACHE_OFFSET_ED (`DCACHE_OFFSET_ST+(`DCACHE_OFFSET_NB)-1)

3
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -123,6 +123,7 @@ module VX_Cache_Bank
wire lw = (i_p_mem_read == `LW_MEM_READ);
wire lb = (i_p_mem_read == `LB_MEM_READ);
wire lh = (i_p_mem_read == `LH_MEM_READ);
wire lhu = (i_p_mem_read == `LHU_MEM_READ);
@@ -137,7 +138,7 @@ module VX_Cache_Bank
wire b2 = (byte_select == 2);
wire b3 = (byte_select == 3);
wire[31:0] data_unQual = b0 ? (data_use[block_offset] ) :
wire[31:0] data_unQual = (b0 || lw) ? (data_use[block_offset] ) :
b1 ? (data_use[block_offset] >> 8) :
b2 ? (data_use[block_offset] >> 16) :
(data_use[block_offset] >> 24);

4
rtl/cache/VX_cache_bank_valid.v vendored
View File

@@ -16,9 +16,9 @@ module VX_cache_bank_valid
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
thread_track_banks[i_p_addr[t_id][2+$clog2(NUMBER_BANKS)-1:2]][t_id] = i_p_valid[t_id];
end
end
endgenerate
endmodule
endmodule

4
rtl/interfaces/VX_dram_req_rsp_inter.v
View File

@@ -11,11 +11,11 @@ interface VX_dram_req_rsp_inter ();
wire [31:0] o_m_evict_addr;
wire [31:0] o_m_read_addr;
wire o_m_valid;
wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
wire o_m_read_or_write;
// Rsp
wire[`DCACHE_NUMBER_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire[`DCACHE_BANKS - 1:0][`DCACHE_NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;