Blaise Tine
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700f9eea19
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moving MUL unit into ALU unit
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2021-02-23 13:49:02 -08:00 |
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Blaise Tine
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143319d557
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minor optimization
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2021-02-18 16:03:16 -08:00 |
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Blaise Tine
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073964fdf7
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minor update
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2021-02-12 08:52:06 -08:00 |
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Blaise Tine
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72b6713a72
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updating fdiv/fsqrt bram hex files, reset_delay updaet
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2021-02-04 09:02:18 -08:00 |
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Blaise Tine
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5419859281
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fcvt fix
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2021-01-25 02:22:00 -08:00 |
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Blaise Tine
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8775f63ec4
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lkg build rollout with 16cores optimization on arria10
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2021-01-24 16:49:22 -08:00 |
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Blaise Tine
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a046bd7a73
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cache pipeline optimization
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2021-01-17 17:19:52 -08:00 |
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Blaise Tine
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ed216ab39d
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minor updates
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2021-01-17 13:58:43 -08:00 |
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Blaise Tine
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d4e7b28be8
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cache refactoring
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2021-01-17 00:18:56 -08:00 |
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Blaise Tine
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ad6e0b4e77
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sp_ram byteen fix
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2021-01-15 16:28:03 -08:00 |
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Blaise Tine
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fe64c47f60
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ccip write fix
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2021-01-14 22:49:06 -08:00 |
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Blaise Tine
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b4b5d6f0ab
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minor updates
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2021-01-12 15:19:38 -08:00 |
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Blaise Tine
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ceae724207
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minor updates
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2021-01-12 11:24:36 -08:00 |
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Blaise Tine
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7e93d253f2
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minor update
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2021-01-10 22:03:23 -08:00 |
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Blaise Tine
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e770824d47
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fixed afu cci write bug, fixed profile cache write miss bug, fixed bram byteenable inferance
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2021-01-10 20:26:15 -08:00 |
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Blaise Tine
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06945533cf
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fixed l2/l3 caches related bugs
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2021-01-09 16:32:55 -08:00 |
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Blaise Tine
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5c83c594c1
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minor update
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2021-01-07 17:25:59 -08:00 |
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Blaise Tine
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146c285aa0
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minor update
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2021-01-06 19:59:04 -08:00 |
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Blaise Tine
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2b8435471a
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speeding up simulation using dedicated full dpi-based FPU core
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2021-01-06 18:44:06 -08:00 |
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Blaise Tine
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39bff921be
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cache bug fixes
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2021-01-05 05:04:49 -08:00 |
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Blaise Tine
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4815ab099c
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using single-port block ram for cache tags, restoring core reset signal
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2021-01-02 19:53:41 -08:00 |
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Blaise Tine
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da9649c2a3
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fixed pipe register reset issue in synthesis
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2021-01-01 14:54:18 -08:00 |
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Blaise Tine
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36602cfa6a
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buffering core reset signal
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2021-01-01 11:46:30 -08:00 |
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Blaise Tine
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d44144f72f
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FPU float<->int conversion optimization
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2020-12-29 15:37:45 -08:00 |
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Blaise Tine
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b2b8f190dd
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minor update
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2020-12-26 14:47:41 -08:00 |
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Blaise Tine
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33c431ed44
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multiplier unit optimization - using fifo for metadata, shift register optimization
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2020-12-26 11:23:21 -08:00 |
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Blaise Tine
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b459192dec
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critical path optimization - fpga fmax @4c = ~212 mhz
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2020-12-26 03:28:32 -08:00 |
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Blaise Tine
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4b7d871d62
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allowing partial cache request submissions, io bus support broken
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2020-12-21 03:53:13 -08:00 |
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Blaise Tine
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4bbd7bf408
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performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,
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2020-12-19 02:45:06 -08:00 |
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Blaise Tine
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3e9abb978b
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fixed typo
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2020-12-09 13:03:22 -08:00 |
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Blaise Tine
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e0905f8352
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minor update
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2020-12-09 05:34:27 -08:00 |
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Blaise Tine
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d81ce8b609
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minor update
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2020-12-09 00:57:31 -08:00 |
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Blaise Tine
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d5fa82f5e4
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cache req datapath optimizations
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2020-12-08 02:58:08 -08:00 |
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Blaise Tine
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1332970636
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refactoring cores clustering
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2020-12-06 14:42:12 -08:00 |
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Blaise Tine
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b2652527bb
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data/dram bus refactoring
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2020-12-06 03:37:22 -08:00 |
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Blaise Tine
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d0f2a3984d
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adding input buffering to bus arbiters to reduce backpressure delay propagation
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2020-12-05 17:31:29 -08:00 |
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Blaise Tine
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13a5370254
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register file refactoring
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2020-12-05 01:40:50 -08:00 |
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Blaise Tine
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478d971389
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minor update
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2020-12-03 16:21:20 -08:00 |
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Blaise Tine
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c3ec4c9e90
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minor update
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2020-12-03 09:30:59 -08:00 |
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Blaise Tine
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f3b1069ce8
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adding stream arbiter
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2020-12-03 06:40:23 -08:00 |
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Blaise Tine
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f575f16f57
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minor update
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2020-12-01 12:57:02 -08:00 |
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Blaise Tine
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b677f724aa
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Use skid buffer on CSR IO bus to stop backpressure delay propagation into csr_unit
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2020-12-01 12:37:15 -08:00 |
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Blaise Tine
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97739e9dcf
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RAM blocks inference fixes
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2020-11-30 14:02:47 -08:00 |
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Blaise Tine
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5758ef9ebf
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generic_register reset network optimization
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2020-11-29 18:41:36 -08:00 |
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Blaise Tine
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ac1883a13f
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tabs cleanup
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2020-11-28 17:08:01 -05:00 |
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Blaise Tine
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eb307edd9c
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minor update
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2020-11-23 17:34:06 -08:00 |
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Blaise Tine
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1795980a52
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L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
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2020-11-21 09:47:56 -08:00 |
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Blaise Tine
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a1fcdd467a
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reset networks optimization
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2020-11-16 01:12:02 -08:00 |
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Blaise Tine
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fceb561cbd
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synchronous reset network optimization: only reset register when required
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2020-11-11 20:54:54 -08:00 |
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Blaise Tine
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725322807e
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fixed DRAM response backpressure inside Cache
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2020-11-10 05:24:57 -08:00 |
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